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Forming Electrical Networks in Three Dimensions by Self-Assembly

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Science  18 Aug 2000:
Vol. 289, Issue 5482, pp. 1170-1172
DOI: 10.1126/science.289.5482.1170

Abstract

Self-assembly of millimeter-scale polyhedra, with surfaces patterned with solder dots, wires, and light-emitting diodes, generated electrically functional, three-dimensional networks. The patterns of dots and wires controlled the structure of the networks formed; both parallel and serial connections were generated.

Most fabrication of microelectronic devices is carried out by photolithography and is intrinsically two-dimensional (2D) (1). The 3D interconnections required in current devices are fabricated by the superposition of stacked, parallel planes and by their connection using perpendicular vias (2–4). We demonstrate self-assembly as a strategy to form interconnections between electronic devices and prefabricated circuits, and to form 3D electrical circuits.

Previous uses of self-assembly to fabricate electronic devices include shape-directed fluidic self-assembly of light-emitting diodes (LEDs) on silicon substrates (5) and coplanar integration of segmented integrated circuit (IC) devices (6) into 2D “superchips” using capillary forces at the surface of a flotation liquid (7). We demonstrate the formation of two classes of 3D electrical networks—parallel and serial—by self-assembly, as an early step toward a strategy for fabricating 3D microelectronic devices. The basic unit in these assemblies is a polyhedron [a truncated octahedron (TO)], on whose faces electrical circuits are printed. In the present demonstrations, these circuits include LEDs to demonstrate electrical connectivity and trace the networks; in the future, they will include devices with more complex functionality (e.g., processors). The LEDs are wired to patterns of solder dots on adjacent faces of the polyhedron. The TOs are suspended in an approximately isodense liquid at a temperature above the melting point of the solder (m.p. ∼ 47°C), and allowed to tumble gently into contact with one another. The drops of molten solder fuse, and the minimization of their interfacial free energy generates the forces that assemble the TOs into regular structures (8). Processes based on capillary interactions between solder drops have been used previously to assemble electronic and mechanical structures: examples include “flip-chip” technology (9) and the rotation of parts of microstructures into nonplanar orientations (10, 11). During assembly, recognition of the pattern of dots on one face by that on another orients and registers the patterns, and generates dot-on-dot electrical connections among polyhedra. Self-assembly of polyhedra can generate networks in which the LEDs are connected either in parallel or in series. Figure 1 outlines both the fabrication of the patterned polyhedra and their self-assembly into 3D structures that include electrical networks (12).

Figure 1

The procedure used to form electrical networks in 3D by self-assembly (12). (A) An array of the basic pattern of copper dots, contact pads, and wires was defined on a flexible copper-polyimide sheet using photolithography and etching. (B) These pattern elements were cut out along the dotted line, (C) glued on the faces of the polyhedron, and (D) LEDs were soldered manually onto the contact pads. (E) The copper dots and wires on the TOs were coated with solder, and self-assembly occurred in hot, isodense, aqueous KBr solution.

We used a scheme in which LEDs were mounted on the hexagonal faces of the TO, and the solder dots were placed on the square faces. To maximize the rate of self-assembly, all of the square faces of the TO had the same fourfold symmetric pattern of solder dots. With this pattern, correct registration of patterns on juxtaposed faces occurred in one of four indistinguishable ways; dots on the patterns that transformed into each other under fourfold rotational symmetry were equivalent and served the same function. On the 3 mm by 3 mm square face, the width of all of the solder dots was ∼1 mm (Fig. 2). A common size was required: the solder wetted the copper with a well-defined contact angle, and each drop of the same size therefore had the same height. Empirical testing suggested that the optimum distance between adjacent solder dots was approximately one-half their width. Smaller separations resulted in electrical shorting between dots due to bridging with solder; larger separations resulted in misalignment. We designed the shapes of solder dots to give an energy diagram for self-assembly having one large (global) minimum and relatively small local minima.

Figure 2

Strategies used to design patterns of solder dots. (A) The widths of all the dots in the patterns used were approximately the same. The width of the wires was smaller. (B) A cross-sectional view [section XX′ in (A)] of two assembling faces. (C) When the faces connect, the solder dots fuse with each other, whereas the wires between them do not touch. (D) A pattern comprising dots that can be used for both parallel and serial networks.

The wires that connect different solder dots electrically on each TO were fabricated in the same way as the dots. When the patterned TOs were dipped in solder, these wires were also covered with a solder layer. By making the wires substantially narrower (∼150 μm) than the diameter of the dots (∼1 mm), we limited the height of the solder film on the wires to ∼15% that of the dots. When the faces self-assembled, the larger dots fused into connections, but the smaller wires did not touch and fuse (Fig. 2C). It was, as a result, unnecessary to insulate the wires to prevent shorting, even when they crossed on juxtaposed faces of two TOs.

We wished to demonstrate, by self-assembly in 3D, networks that are widely used in current 2D IC technology. In these systems, pins on processors belong to one of three groups: bus lines (driving voltage, clock), inputs, and outputs. Bus lines connect processors in parallel; outputs of one processor connect serially to inputs of adjacent processors.

In the pattern of solder dots (Fig. 2D), the five dots that lie on reflection axes comprise two sets of dots differentiated by symmetry: {1} and {2, 5, 8, and 11}. During self-assembly, dots from one set on a TO connect to dots from the same set on another TO. These dots are used for parallel or bus-line connections. The other dots, {3, 6, 9, and 12} and {4, 7, 10, and 13}, form two distinct sets related by reflection symmetry. Upon assembly, dots from one set on a TO (e.g., outputs from one processor) connect to those from the other set on another TO (e.g., inputs to a second processor). These dots are used for serial, input/output connections.

Figure 3 shows the realization of a 3D network with parallel connectivity, using self-assembly. The pattern of solder dots consisted of dots {2, 5, 8, and 11} and {1} (Fig. 2D), which were on the axes of symmetry of the square face (13). In the assembled aggregate, LEDs on one TO connected to those on the adjacent TO in parallel, along three orthogonal directions. The fidelity of the interconnections was visualized by lighting up the LEDs connected in parallel in the assembly. This self-assembled, 3D parallel network mimicked bus lines in circuits in which a number of electrical components are powered by the same common wires.

Figure 3

(left). A self-assembled 2 × 2 × 3 aggregate containing 12 TOs and demonstrating parallel connectivity. (A) The pattern of copper dots, wires, and contact pads used. (B) A patterned TO with three LEDs, prior to assembly. (C) A photograph of the self-assembled aggregate and a penny (to indicate size). Two electrically isolated pairs of wires connected to a battery illuminate six LEDs in an electrically continuous loop involving three TOs. (D) Circuit diagram showing the parallel network formed. The gray circles represent individual TOs. The blue half-circles represent solder dots that connect on juxtaposed faces of two TOs. The LEDs are shown in black. The network contains 16 pairs of wires, which consist of four (red), six (green), and six (blue) pairs in each of the three dimensions. The six LEDs that illuminate are highlighted by black squares

For the realization of a 3D network with serial connectivity (Fig. 4), we used the sets of solder dots {3, 6, 9, and 12} and {4, 7, 10, and 13} (Fig. 2D) that were off the axes of symmetry of the square face (14). The important feature of the assembled 3D network was that the cathode of one LED always connected to the anode of another LED across the assembling faces. The serial networks were traced by illuminating sets of LEDs (e.g., Fig. 4D) (15).

Figure 4

(right). A self-assembled 2 × 2 × 3 aggregate containing 12 TOs and demonstrating serial connectivity. (A) The pattern of solder dots used. (B) The terminals of a single LED are directly soldered across two contact pads, and a wire is soldered in a way that connects the third contact pad to one of the terminals of the LED, using a polarity in which the anode of the LED connects to dots from the set {3 and 9} and the cathode connects to dots from the set {7 and 13}. (C) A patterned TO prior to assembly. (D) A self-assembled aggregate. The LEDs on different TOs connect to each other in serial loops. The loops were traced by powering pairs of leads. Individual loops range in size from those containing two LEDs to one that contains 10 LEDs; this loop is shown illuminated. (E) The circuit diagram sketching the largest serial loop formed; 10 LEDs illuminate when the loop is connected to a battery (D). The LEDs connect cathode to anode in all loops.

The 3D assemblies can be designed to be porous: this porosity may allow for cooling fluid to be pumped through the assemblies. The shape and the distribution of solder dots on the assembling faces raises interesting questions regarding the design of patterns that best enable the “recognition” of one pattern by another. Other concepts adapted from 2D self-assembly, such as hierarchical self-assembly (16) and shape-selective self-assembly [that is, use of lock-and-key structures (17, 18)], offer more sophisticated strategies for the fabrication of asymmetrical networks incorporating more than one repeating unit.

We have demonstrated parallel and serial connectivity separately; it is possible to extend these ideas to more complex networks involving different combinations of parallel and serial connections. The LEDs in our demonstrations are simple bipolar electronic devices; to fabricate 3D computational devices, we must incorporate elements of digital logic [e.g., five-pin, single-logic gates (19)]. Self-assembly facilitates the formation of highly interconnected elements in both deterministic and probabilistic networks; it may be possible to use this kind of self-assembly to generate other logical structures (e.g., artificial neural networks) (20).

We have carried out all experiments using only a limited number of polyhedra: to extend this approach to a larger number of elements, and to smaller elements, it will be necessary to develop practical methods for fabricating these elements; the need for 3D microfabrication permeates 3D self-assembly, but new methods are beginning to emerge (21–24). Although large arrays may have defects, it may be possible to develop computational algorithms even in defective networks (25–28).

  • * To whom correspondence should be addressed. E-mail: gwhitesides{at}gmwgroup.harvard.edu

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