As the trend to shrink the feature size of integrated electronic devices continues, and circuit design becomes more three-dimensional, there is also an accompanying practical issue to address, which relates to maintaining the compatibility of the mechanical and electrical isolation layers and materials. The role of such barrier layers is vital in preventing the electrical lines from shorting and the devices from failing due to copper diffusing into the active region of the devices. For future device fabrication sizes of 45 nm, it is expected that the present barrier technology based on TaN will not be effective and that a new approach will be required. Mikami et al. have investigated self-assembled monolayers (SAMs) for this purpose. They fabricated simple capacitive devices and looked at their lifetime under the thermal and electrical stresses of typical operating conditions. Their results show that a SAM layer just 1.7 nm thick is a sufficient barrier to copper diffusion and that the estimated lifetime of such a barrier layer should be in excess of 10 years. — ISO
Appl. Phys. Lett. 83, 5181 (2003).