A million spiking-neuron integrated circuit with a scalable communication network and interface

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Science  08 Aug 2014:
Vol. 345, Issue 6197, pp. 668-673
DOI: 10.1126/science.1254642

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  1. Fig. 1 Computation, communication, and memory.

    (A) The parallel, distributed architecture of the brain is different from the sequential, centralized von Neumann architecture of today’s computers. The trend of increasing power densities and clock frequencies of processors (29) is headed away from the brain’s operating point. Number and POWER processors are from IBM, Incorporated; AMD, Advanced Micro Devices, Incorporated; Pentium, Itanium, and Core 2 Duo, Intel, Incorporated. (B) In terms of computation, a single processor has to simulate both a large number of neurons as well as the inter-neuron communication infrastructure. In terms of memory, the von Neumann bottleneck (15), which is caused by separation between the external memory and processor, leads to energy-hungry data movement when updating neuron states and when retrieving synapse states. In terms of communication, interprocessor messaging (25) explodes when simulating highly interconnected networks that do not fit on a single processor. (C) Conceptual blueprint of an architecture that, like the brain, tightly integrates memory, computation, and communication in distributed modules that operate in parallel and communicate via an event-driven network.

  2. Fig. 2 TrueNorth architecture.

    Panels are organized into rows at three different scales (core, chip, and multichip) and into columns at four different views (neuroscience inspiration, structural, functional, and physical). (A) The neurosynaptic core is loosely inspired by the idea of a canonical cortical microcircuit. (B) A network of neurosynaptic cores is inspired by the cortex’s two-dimensional sheet. (C) The multichip network is inspired by the long-range connections between cortical regions shown from the macaque brain (30). (D) Structure of a neurosynaptic core with axons as inputs, neurons as outputs, and synapses as directed connections from axons to neurons. Multicore networks at (E) chip scale and (F) multichip scale are both created by connecting a neuron on any core to an axon on any core with point-to-point connections. (G) Functional view of core as a crossbar where horizontal lines are axons, cross points are individually programmable synapses, vertical lines are neuron inputs, and triangles are neurons. Information flows from axons via active synapses to neurons. Neuron behaviors are individually programmable, with two examples shown. (H) Functional chip architecture is a two-dimensional array of cores where long-range connections are implemented by sending spike events (packets) over a mesh routing network to activate a target axon. Axonal delay is implemented at the target. (I) Routing network extends across chip boundaries through peripheral merge and split blocks. (J) Physical layout of core in 28-nm CMOS fits in a 240-μm-by-390-μm footprint. A memory (static random-access memory) stores all the data for each neuron, a time-multiplexed neuron circuit updates neuron membrane potentials, a scheduler buffers incoming spike events to implement axonal delays, a router relays spike events, and an event-driven controller orchestrates the core’s operation. (K) Chip layout of 64-by-64 core array, wafer, and chip package. (L) Chip periphery to support multichip networks. I/O, input/output.

  3. Fig. 3 Real-time multiobject recognition on TrueNorth.

    (A) The Neovision2 Tower data set is a video from a fixed camera, where the objective is to identify the labels and locations of objects among five classes. We show an example frame along with the selected region that is input to the chip. (B) The region is transduced from pixels into spike events to create two parallel channels: a high-resolution channel (left) that represents the what pathway for labeling objects and a low-resolution channel (right) that represents the where pathway for locating salient objects. These pathways are inspired by dorsal and ventral streams in visual cortex (4). (C) What and where pathways are combined to form a what-where map. In the what network, colors represent the spiking activity for a grid of neurons, where different neurons were trained (offline) to recognize different object types. By overlaying the responses, brighter colors indicate more-confident labels. In the where network, neurons were trained (offline) to detect salient regions, and darker responses indicate more-salient regions. (D) Object bounding boxes reported by the chip.

  4. Fig. 4 Benchmarking power and energy.

    (A) Example network topology used for benchmarking power at real-time operation. Nodes represent cores, and edges represent neural connections; only 64 of 4096 cores are shown. (B) Although power remains low (<150 mW) for all benchmark networks, those with higher synaptic densities and higher spike rates consume more total power, which illustrates that power consumption scales with neuron activity and number of active synapses. (C) The total energy (passive plus active) per synaptic event decreases with higher synaptic density because leakage power and baseline core power are amortized over additional synapses. For a typical network where neurons fire on average at 20 Hz and have 128 active synapses [marked as * in (B) and (C)], the total energy is 26 pJ per synaptic event.