Nanomaterials in transistors: From high-performance to thin-film applications

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Science  14 Aug 2015:
Vol. 349, Issue 6249, aab2750
DOI: 10.1126/science.aab2750

Improving transistors with nanomaterials

High-performance silicon transistors and thin-film transistors used in display technologies are fundamentally limited to miniaturization. Incorporating nanomaterials—such as carbon nanotubes, graphene, and related two-dimensional materials like molybdenum disulfide—into these devices as gate materials may circumvent some of these limitations. Franklin reviews the opportunities and challenges for incorporating nanomaterials into transistors to improve performance. Because high-performance transistors are distinct from thin-film transistors, incorporating them into flexible or transparent platforms raises new challenges.

Science, this issue 10.1126/science.aab2750

Structured Abstract


Transistors are one of the most enabling “hidden” technologies of all time and have facilitated the development of computers, the Internet, thin mobile displays, and much more. Silicon, which has been the material of choice for transistors in nearly every application for decades, is now reaching the fundamental limits to what it can offer for future transistor technologies. The newest display technologies are already turning to metal oxide materials, such as indium gallium zinc oxide (IGZO), for the improvements needed to drive organic light-emitting diodes. Ranging from applications such as display backplanes to high-performance microprocessors for servers, nanomaterials offer lasting advantages for the coming decades of transistor technologies. In this Review, the advantages of nanomaterials are discussed in the context of different transistor applications, along with the breakthroughs needed for nanomaterial transistors to enable the next generation of technological advancement.


About 15 years ago, nanomaterials began receiving focused attention for transistors. Carbon nanotubes—molecules consisting of a cylindrical single layer of carbon atoms arranged in a hexagonal lattice—were the first to be given serious consideration, and their benefits quickly became widely acclaimed. Given their ability to transport electrical current with near-zero resistance, even at room temperature, the explosion of interest in nanotubes for electronics was understandable. Graphene, a related allotrope of carbon, benefited from the expansive interest carbon nanotubes had created for nanomaterial electronics. Although graphene transistors eventually proved less viable for digital applications, owing to the absence of an energy band gap, the excitement over graphene ushered in a complete revolution of interest in similar two-dimensional materials. Now, transition metal dichalcogenides and the so-called X-ene family of nanomaterials (e.g., silicence, phosphorene) dominate the attention of the nanoelectronics community. Hardly a day goes by without a paper being published on some advancement related to the use of nanomaterials in transistors. Hence, this Review focuses on how to keep such progress in the proper context with respect to the target transistor application, as well as the consideration of nanomaterials for completely new application spaces.


The benefits and practicality differ for each nanomaterial, and varied amounts of progress have been made in considering each of them for transistors. In just a few short years, thousands of papers have been published on improving synthesis or demonstrating simple functions of the newer nanomaterials. However, reflection on whether their newness translates to actual superiority over other options is warranted. Clearly, all of the nanomaterial possibilities offer certain advantages for future transistor technologies, but some do so with fewer caveats than others. Future research will benefit from keeping scientific advancement of nanomaterial transistors in line with end-goal deliverables. Overall, considering that only 15 years have elapsed since the study of nanomaterials for transistors began in earnest, the toolbox of available options and the developments toward overcoming challenges are promising.

Technologies enabled by high-performance and thin-film transistors over the past 25 years.

(Top) Silicon transistors have driven the microprocessors used in computational devices ranging from low-power gadgets to large servers. (Bottom) Various forms of cheaper silicon enabled the display revolution, now being shared by IGZO. (Right) Nanomaterials may be the next transistor material for enabling a new generation of technologies.

CREDITS: Old computer: Wikimedia Commons/Creative Commons; Other computer: J.Dray/Flickr; Laptop: C. Berkeley/Flickr; Supercomputer: Wikimedia Commons/Creative Commons; Smartphone: Pixabay/Creative Commons; Camera: DAYJOY/Flickr; FLAT SCREEN TV: AV Hire London/Flickr; Curved TV: SamsungTomorrow/Flickr


For more than 50 years, silicon transistors have been continuously shrunk to meet the projections of Moore’s law but are now reaching fundamental limits on speed and power use. With these limits at hand, nanomaterials offer great promise for improving transistor performance and adding new applications through the coming decades. With different transistors needed in everything from high-performance servers to thin-film display backplanes, it is important to understand the targeted application needs when considering new material options. Here the distinction between high-performance and thin-film transistors is reviewed, along with the benefits and challenges to using nanomaterials in such transistors. In particular, progress on carbon nanotubes, as well as graphene and related materials (including transition metal dichalcogenides and X-enes), outlines the advances and further research needed to enable their use in transistors for high-performance computing, thin films, or completely new technologies such as flexible and transparent devices.

Fifty years ago, Gordon Moore published his seminal paper that included a projection that the semiconductor industry would double the number of components on a chip (integrated circuit) roughly every couple of years (1). Although slightly modified over time, this projection from one of Intel’s founders has served as the marching orders for what is now a >$330 billion global industry (2) and has been given the moniker “Moore’s law.” Notable innovations have allowed the silicon metal oxide semiconductor field-effect transistor (MOSFET) to be made smaller, the latest being from strained-silicon channel materials to three-dimensional (3D) fin gate structures, as depicted in Fig. 1C. Despite these advances, fundamental physical limits for the minimum size of silicon MOSFETs are now being approached, and the question of “what’s next” for transistors has become inescapable.

Fig. 1 High-performance transistors versus TFTs: Moore’s law and device comparison.

(A) Approximate plot of Moore’s law, showing increasing density of integrated transistors (reduction of transistor size). High-performance transistors exhibit the traditional trend, with a density that doubles approximately every 2 years, whereas there has been little change in the approximate density of TFTs. (B) A different view of Moore’s law, showing the approximate substrate or die size for the two transistor technologies over time (TFT substrate size is based on display applications and has doubled every ~2.5 years). For (A) and (B), lines are approximate fits to actual data, as in (3, 4). (C) Cross-sectional schematics comparing the general structure of high-performance transistors and TFTs with silicon versus nanomaterial channels. Note that the latest high-performance silicon device could consist of fins (3D) or nanowire channels, as shown. Also indicated is the channel length Lch for each device. In the nanomaterial channel transistors, where the channel is made up of 1D or 2D nanomaterials, there is little difference in structure between high-performance transistors and TFTs, yet size differs by orders of magnitude—a key source of confusion in the field. S, source; G, gate; D, drain.

The microprocessor, now driven by billions of MOSFETs on a single chip, is the most prominent transistor application, as it is the computational “brain” to every electronic system. Yet there are other needs for the transistor that do not necessarily require the high performance (and high cost) of MOSFETs—for example, chemical and biological sensors, optical detectors, and the pixel-driving circuits for displays. Aside from the microprocessor, the most prominent use of transistors is in the backplane electronics of flat-panel displays. Departure from the cathode ray tube was made possible, in part, by the use of low-cost amorphous silicon (a-Si) thin-film transistors (TFTs) in liquid-crystal displays.

That a-Si TFTs were made from silicon is one of very few attributes TFTs have in common with silicon MOSFETs. MOSFETs are generally high-performance and high-cost transistors used for computational devices (e.g., smartphones, computers, servers), whereas TFTs are less cost intensive and are used in applications with much lower performance requirements. Consider the different perspectives on Moore’s law shown in Fig. 1 for these two types of transistors. The traditional Moore’s law in Fig. 1A is obeyed by high-performance transistors, wherein the density of devices doubles approximately every 2 years (3). For TFTs, the integration density has changed relatively little, with the focus being more on improving stability and driving down cost. The Moore’s law perspective in Fig. 1B focuses on the component substrate size (4); here, the trend for TFTs is based on the display market, where the ability to fabricate large areas of transistors is crucial (5). Meanwhile, the die size of the MOSFET—the area of a single chip on a much larger production wafer—has been capped at ~300 mm2 to minimize production costs by yielding more chips per wafer. Overall, these two perspective plots highlight the importance of recognizing the differences in applications and deliverables between high-performance transistors and TFTs.

Nanomaterials are of great interest for use in transistors of all types, as they offer many electrical and mechanical advantages. Unlike silicon-based transistors, the general structure of a nanomaterial transistor changes very little between the high-performance and thin-film varieties, except in size (see Fig. 1C). This similarity has led to much confusion in the research community as to whether certain reported nanomaterial transistor advancements are useful for high-performance or thin-film applications. Such confusion occurs only for nanomaterials, as the silicon community developed different materials expressly for TFTs. Consider the substantial difference in target performance metrics—often orders of magnitude—between high-performance transistors and TFTs (from any material), as shown in Table 1. In this Review, in addition to considering the great progress and promise in the field of nanomaterial transistors, clarification of this important distinction between the intended application spaces will be provided. Guided by an understanding of the relevant dimensional and performance targets (see Table 1), it is hoped that future research on nanomaterial transistors can more accurately address the scientific challenges limiting their ultimate realization.

Table 1 Comparison of key target metrics for high-performance transistors and TFTs.

Channel length is defined in Fig. 1 and is critical for the packing density of transistors. Ion indicates the on-state performance, including transistor speed. VDD reflects the off-state performance, with lower VDD needed for densely integrated high-performance applications. Mobility is discussed below and has become relevant only for TFTs. Process complexity is given in terms of the number of mask layers or levels used to fabricate the transistors. Although this number will vary for high-performance transistors, depending on the application (digital logic versus memory, server chip versus low-power system-on-chip, etc.), the approximate average is given and clearly shows the advantage for TFTs with <20% the process complexity. Cost for fabrication line or facility (fab) is based on the most recent facilities reported—and the numbers for TFTs are for fabs that produce full OLED displays (not just the TFT backplane)—yet it is still considerably cheaper than a high-performance transistor fab. The dash indicates no ability to numerically compare.

View this table:


The term “nanomaterial” can refer to any material with dimensions at the nanoscale (<100 nm), but for transistor applications, the materials that naturally exhibit quantum confinement and occur without the need for thinning or patterning are of greatest interest. Hence, the focus of this Review will be on such naturally quantum-confined nanomaterials, including single-walled carbon nanotubes (CNTs), graphene, transition metal dichalcogenides (TMDs), and X-enes (the newest and least naturally occurring variant of 2D crystals, typically consisting of a buckled hexagonal structure to mimic graphene—hence the name “X-ene”; examples include phosphorene for phosphorous and silicene for silicon). There certainly are benefits in transistors from other types of nanomaterials, such as nanowires (6, 7), which are nanoscale versions of bulk materials. However, it is typically best to avoid quantum confinement in such materials rather than embrace it as a key aspect of their electronic structure because it would introduce considerable variation in the resulting device performance and degrade carrier transport properties. Most of the nanomaterials discussed herein are often classified as van der Waals materials, as they do not covalently or ionically bond to other materials but exist as 1D or 2D constituents that are either isolated or assembled in some fashion via van der Waals weak attraction forces.

Extensive articles reviewing the distinctive properties of each of these nanomaterials have been published (815); as the focus of this Review is on the use of the nanomaterials in transistors, only a brief summary of their key attributes is given. Of note is that single-walled CNTs and graphene share the sp2-bonded, hexagonal carbon lattice and thus exhibit similar carrier transport properties, including high Fermi velocity (vF), which can lead to higher switching speeds. Low effective mass and correspondingly high carrier velocity make CNTs and graphene the most ideal electron transport systems available. Consequently, CNTs are favorable options for very small transistors that can operate at low voltages, thus conserving power, because silicon-based transistors suffer degradation in performance (e.g., leakage currents) when operated below ~1 V. The nanotubes, which can be conceptualized as rolled up sheets of graphene, are circumferentially quantum-confined, which makes them true 1D electronic systems with reasonable energy band gaps that allow them to turn off with little leakage current. The lack of an energy band gap in graphene is the nanomaterial’s greatest pitfall for transistors, rendering the devices unable to block current flow and be switched to the off state (digital “0”). Great efforts have been made to induce a band gap in graphene (16, 17), but to date, they lack practicality. Even thinning graphene to create quasi-1D nanoribbons (18, 19) to create a band gap still has disadvantages, such as edge states, compared with the naturally 1D nanotubes. The most likely use of graphene in digital transistors arises from its ability to enable distinct 2D heterostructures, which will be discussed below. A summary of some of the most relevant intrinsic properties of these nanomaterials for electronics applications is given in Fig. 2. Note that the focus in Fig. 2 is not given to mobility or extrinsic device metrics, such as contact resistance, as these are only relevant in certain devices or are highly variable, depending on specific interfacial materials. Further discussion of such other metrics is given below.

Fig. 2 Nanomaterial options for transistors.

A comparison of key intrinsic attributes of the four most prominent nanomaterials (or families of nanomaterials) is shown contrasted with the related attributes of silicon. Carbon nanotubes and graphene share the sp2 bond structure and thus many electrical transport properties, with the exception that the nanotubes are circumferentially quantum confined to form 1D cylinders with band gaps. The TMDs that are most amenable for transistors are the Mo and W families (e.g., MoS2, WSe2). X-enes, typically consisting of a buckled hexagonal structure and lacking stability in air, are the newest and least naturally occurring variant of 2D crystals. The channel or body thickness (dbody) limit for silicon is based on the onset of quantization effects that must be avoided for a bulk material. Eg, band gap; m0, electron rest mass; vsat, saturation velocity; vF, Fermi velocity.

The interest in studying graphene for transistors spurred reconsideration of a very well-known class of van der Waals nanomaterials that had not been studied for electronics in many years: TMDs. Many combinations of transition metals (e.g., Mo, W, Hf) and chalcogens (e.g., S, Se, Te) can yield the three-atom-thick arrangement of a monolayer TMD (9). For transistors, the greatest interest has been in the Mo and W families, especially MoS2. Electron transport in TMDs is slower by a factor of 20 compared with carbon nanomaterials, but TMDs offer sizable energy band gaps for switching and maintain the attractive 2D confinement of graphene. If more than one monolayer is stacked to form a many-layer TMD, the band gap changes markedly, typically saturating to approximately the bulk value at ~15 layers with a gap that is barely two-thirds that of the monolayer.

Most recent to join the options of nanomaterials for transistors is the so-called X-ene family (2026). Exploration began a few years ago, motivated by the electronic structure of graphene, including a linear dispersion relation of Dirac cones, for other group IV and V nonmetals arranged in a similar fashion to the graphene hexagonal lattice. Thus far, demonstrations of silicene (silicon) (21), germanene (germanium) (24), phosphorene (black phosphorus) (23, 25, 26), stanene (tin) (20), and arsenene (arsenic) (22) have been made. Their lattice structures are not as perfectly planar hexagonal as that of graphene but tend to be some variation in a buckled hexagonal form (20). Phosphorene exhibits van der Waals stacking, but the other X-enes are synthesized as adlayer structures on certain substrates. Limited experimental work has been performed on X-enes, but theoretical projections indicate potentially attractive electronic properties, including the presence of a reasonable band gap and transport behavior about half as favorable as that of graphene (Fig. 2). One of the biggest challenges for X-enes compared with other nanomaterials is that X-enes tend to be highly reactive in air, making even simple device structures extremely difficult to realize (21).

To consider the progress that has been made in demonstrated nanomaterial transistors, a summary of a few key device metrics is given in Fig. 3A. For high-performance transistors, there is a need to scale the channel length Lch and contact length Lc while operating at low voltage VDD. Note that the approximate progress shown for each metric in Fig. 3A is from diverse reports; in other words, there has yet to be a solution that shows the scaling of all relevant dimensions along with low-voltage operation. As will be discussed below, the focus for TFTs is on mobility μ and on-state current Ion, where nanomaterials have already shown substantial improvements over silicon-based options. Based on the Fig. 3A comparisons, CNTs show the most consistent promise thus far, which is partly an artifact of their being studied the longest but also undoubtedly related to their superior carrier transport properties compared with the TMDs or X-enes. These metrics are certainly notcomprehensive, but when considering any of these nanomaterials for the indicated applications, such target deliverables must be kept in mind.

Fig. 3 Performance comparison, benefits, and challenges for nanomaterials in transistors.

(A) Approximate comparison of demonstrated performance or device metrics, where Lch is channel length and Lc is contact length (length over which the metal contact covers the nanomaterial). Note that the approximate values for the nanomaterials are from reports involving transistors with relevant dimensions and structure, and the metrics would need to be simultaneously met (along with others not included) for the targeted transistor technology. Also shown are the approximate values for the most advanced transistors from silicon-based materials. (B) Overview of transistor benefits offered by all nanomaterials, including atomic thinness, substrate independence, potential for heterostructures, and distinctive electronic properties. E, energy; k, wave number. (C) Overview of challenges shared in some fashion by all nanomaterials for transistors, including high-quality synthesis, controlled placement, improved interfaces (contact and dielectric), and devices that more fully utilize nanomaterial advantages.

Benefits of nanomaterials

Despite the substantial differences in intrinsic properties among the nanomaterial options, they have common advantages for transistors, as summarized in Fig. 3B. Foremost, nanomaterials are all atomically thin. For high-performance transistors, there is a need to scale the channel length to sub–10-nm dimensions because this will be required for technologies targeted for the early 2020s, and silicon is unable to operate at such length scales. Such scaling requires the transistor gate to maintain electrostatic control over the channel—a difficult feat when the channel thickness (dbody) is greater than Lch. The atomic thinness of nanomaterials, especially in their monolayer form for 2D nanomaterials, offers ideal electrostatic control. Often the ultimate scalability of a transistor with an undoped (intrinsic) channel—such as all nanomaterials shown in Fig. 2—is determined by the screening or natural length λ being proportional to dbody. The rule-of-thumb is that a Lch ≥ 3λ will ensure that the gate maintains electrostatic control and that deleterious short-channel effects are avoided (27).

Another benefit shared by most nanomaterials is their substrate independence. CNTs can be synthesized in a reactor chamber, dispersed in solution to isolate a certain diameter or energy band gap (2838), and then deposited onto any substrate of choice, all while keeping their crystal structure and transport properties intact. The same is true for graphene and TMDs, with the exception of X-enes, as they are generally substrate-bound (except for phosphorene). Although synthesis conditions are extreme in most cases, the ability to transfer nanomaterials to virtually any substrate and fabricate transistors from them is one of their greatest strengths.

Heterostructures of the nanomaterials in Fig. 2 are becoming an attractive possibility for transistors, including the use of all 2D nanomaterials for fabricating transistors (e.g., graphene contacts, TMD channel, and hexagonal boron nitride gate dielectric) (3941), as well as the stacking of diverse TMDs in a fashion similar to epitaxial III-V materials (4249). Work continues on understanding what governs transport at these nanomaterial heterostructure junctions. Several devices that make explicit use of such heterostructures in their operation have been demonstrated, and it will be exciting to see the types of new transistors this approach will enable.

Other strengths that nanomaterials offer for transistors typically depend on device structure or type. For instance, the presence of a small quantum capacitance (dependent on the density of states), especially in CNTs, has been shown to enable more extensive modulation of the surface potential in the on state of a transistor (50). Operation in this quantum capacitance limit is of great value for tunneling transistors, for which the thinning of tunnel barriers to achieve higher current is crucial. Other nanomaterial properties that are useful for specific devices include spin transport, Coulomb blockade, charge density waves, and plasmons, but the focus of this Review will be on more conventional digital transistors.

Challenges for nanomaterials

Just as the nanomaterials in Fig. 2 share many advantages for transistors, they also have challenges in common, as summarized in Fig. 3C. Without question, the biggest challenges relate to the controlled synthesis and placement of the nanomaterials. Although there has been widely varied progress on addressing the synthesis and placement challenges among the different nanomaterials, they all require substantial improvement to be viable for a transistor technology. Synthesis of nanomaterials takes place at high temperatures (typically >800°C). In most cases, the nanomaterials are synthesized on a sacrificial substrate and then transferred in some fashion to the substrate for fabricating transistors. Whether or not they are kept on their synthesis substrate, the distribution in dbody (diameters for CNTs and number of layers for 2D nanomaterials) must also be controlled. Tremendous progress has been made in separating CNTs of certain electronic type (band gap in CNTs is dependent on dbody) (2838), which indicates promise for reaching technology targets so long as scientific investment continues (current highest verified purity is 99.99% with a target of 99.9999%) (51). Progress has also been made in synthesizing TMDs (5260), although there has yet to emerge a process capable of growing a TMD with complete coverage, high quality (low defect and grain boundary density), and a uniform number of layers. Being the newest explored nanomaterial and not exhibiting van der Waals stacking behavior, X-enes have the farthest to go for improved synthesis.

If the nanomaterial is synthesized on one substrate and then transferred to another for transistor fabrication, then precision placement is important. For CNTs, this problem is especially pronounced, as they require accurate positioning into arrays. The target pitch for CNTs in high-performance transistors is 5 to 8 nm (125 to 200 CNTs per micrometer) (13), and promising advancements continue to be made to this end (6168), including the use of selective deposition to predefined regions of a substrate (50-nm pitch achieved). It is less favorable to have tightly packed (~0-nm pitch) arrays of CNTs for high-performance transistors (62), as they will result in deleterious charge screening effects and challenges for establishing good electrical contacts. Requirements for TFTs are much more relaxed, where even tangled films of CNTs with no alignment can be used (6971). The 2D nanomaterials do offer planar coverage, but it is difficult to transfer the films without inducing defects that are detrimental to transistor performance. An additional complication for X-enes is their pronounced dependence of carrier transport on crystallographic direction (23); orientation of the X-ene film will change the effective mass of the carriers by up to one order of magnitude.

Interfaces to nanomaterials are another challenge. Without having available surface states in the way that bulk materials do, the formation of covalent bonds to nanomaterials can be difficult. For instance, nucleating the growth of high-quality dielectrics (insulating barriers) with atomic layer deposition (ALD) is problematic for nanomaterials, as they do not offer typical end groups for reacting with the ALD precursors. Creative solutions have been presented for potentially addressing the creation of high-quality dielectric interfaces (7275), but there has been much less progress on improving the contact metal interfaces. Regardless of whether a nanomaterial transistor is for high-performance or thin-film applications, the device will depend heavily on the quality of transport at the source and drain metal contact interfaces. Studies have been performed on the impact of different metals on the contact resistance for CNTs (7678), TMDs (7981), and even X-enes (82), most of which consider the metal-nanomaterial interface as a traditional Schottky barrier structure. However, with no covalent bonding between the metal and nanomaterial, the reality of what determines transport at the interface remains elusive, and the Schottky barrier picture has been shown to break down under certain conditions (78).

In all cases, the metal-nanomaterial contact interface requires further scientific study and engineering improvement to yield the necessary performance and consistency for a transistor technology. Many have interpreted this to simply mean the achievement of low contact resistance (Rc), but depending on the transistor application, realizing a low Rc may not address all of the relevant contact issues, including scalability and reproducibility. For example, for high-performance transistors with contact lengths <15 nm (see Fig. 3A), the target Rc must be <150 ohm·μm (measured contact resistance multiplied by device width) per contact (78)—a substantial challenge even at very long (>200-nm) contact lengths.

A final point regarding challenges for nanomaterials in transistors is the need for further discovery and innovation of the transistor structures. Thus far, nanomaterials are integrated into transistors that essentially mimic the silicon MOSFET, especially for high-performance applications (Fig. 1). Considering their substrate independence, there are undoubtedly much more favorable transistor structures that have yet to be discovered for nanomaterials. Such structures would take more specific advantage of the electrical and mechanical properties of nanomaterials for boosting performance, lending new functionality, or both for certain applications. Additionally, regardless of the transistor structure into which nanomaterials are integrated, a need remains for studying the reliability of resultant devices and circuits to ensure their utility under certain application requirements, such as high clock speeds.

High-performance transistors

High-performance transistors are those that enable the primary computing electronics that we rely on daily. Servers that fill warehouses (server farms) are the lifeblood of the Internet and rely on the highest-performing scaled transistors. Semiconductor companies such as Intel and Taiwan Semiconductor Manufacturing Company will develop the transistor technology—for example, “14 nm” (83)—for the highest-performance applications and then use mostly the same transistor for other less-demanding applications. An example is the low-power chips that are used for mobile electronics (e.g., smartphones, tablets, laptops), where the chip will still make use of transistors with the latest technology (14 nm) but will be integrated less densely and run at lower voltages. In this case, the term “high-performance transistor” refers to the transistor technology itself that is applied to all such peripheral applications—from servers to smartphones.

A closer look at Moore’s law for high-performance transistors, given in Fig. 4, helps to highlight why nanomaterials are so advantageous. In the early 2000s, the performance (as measured by chip clock frequency) was necessarily capped to address the runaway power density problem (84): Smaller transistors could leak power even in the off state, leading to power-consumption and heat-generation issues. Anything beyond ~100 W/cm2 is detrimental to the chip and surrounding components; heating a semiconductor causes performance fluctuations, and the ability for cooling technologies to dissipate the heat is limited to ~100 W/cm2. Active power (PA) depends on clock frequency (f), operating voltage (VDD), and the number of transistors per square centimeter (N) as PA α N*f*(VDD)2. With Moore’s law demanding that N continue to increase, the most logical solution would be to reduce VDD because of the squared dependence. However, the cost in terms of performance was too great, and VDD has remained pegged for more than a decade at ~1 V for high-performance transistors. Reducing f would also seriously compromise performance, leading to the need for multicore architectures. The advantage of multicore chips in terms of the power problem is that the architecture ensures that, at any given time, a much smaller fraction of the transistors will be turned to the on state than for a single core chip—a phenomenon known as dark silicon (85). However, the multiplication of the number of cores will hit a level of maximized benefit at ~16 cores, leaving reduction of VDD the only hope for further progress.

Fig. 4 Detailed look at Moore’s law for high-performance transistors.

Approximate plot of various metrics in high-performance microprocessors over the past >40 years [lines are approximate fits to actual data, see (3)]. The oft-quoted version of Moore’s law is the number of transistors per chip (black line), but key trade-offs in chip performance (clock frequency, blue curve) have been made since the early 2000s because of the power density (red curve) reaching a physical limit of ~100 W/cm2. Continued Moore’s law scaling of high-performance transistors has been sustainable only by multicore architectures (green curve)—and the associated “dark silicon”—for the past decade.

Nanomaterials offer several ways of reducing the operating voltage in high-performance transistors. First, their atomic thinness enables highly effective gate control over the channel potential through the reduced screening length discussed above. Improved gate control means that even at aggressively scaled channel lengths (needed for driving an increase in N), nanomaterial transistors can switch to the on state at the lowest possible voltages (i.e., small subthreshold swing, which is an indicator of how many volts are required to switch the current in a transistor by one order of magnitude). The subthreshold swing is referred to as the performance metric in the off state, indicating the ability of a transistor to switch at low voltages. Beyond improved gate control, nanomaterials also enable advanced transistor structures that may offer solutions for scaling VDD. One such option is the tunneling transistor, where the small effective mass (me) in CNTs (as well as some 2D options) would offer dramatic improvement (increase) in the tunneling current to boost the on state, which limits the realization of these transistors (86, 87).

Exceptional electron transport in most nanomaterials is another attractive feature for high-performance transistors. In the case of CNTs, nearly ballistic (zero resistance) transport has been observed at room temperature at lengths up to 40 nm (88, 89). Such favorable transport has experimentally been shown to enable sub–10-nm CNT transistors that outperform any similarly scaled silicon-based transistor at low voltages (VDD ≤ 0.5 V) (90). Transport in TMDs is actually worse than in most bulk semiconductors, including silicon; yet at sufficiently scaled channel lengths, TMDs could still offer advantages, as performance in the transistor will become dominated by contacts rather than transport through the channel. For the required dimensions of a high-performance transistor, the performance of every device will be determined more by the contacts than by the channel, regardless of whether it is a nanomaterial or silicon or any other semiconductor. For this reason, the use of the prevalent transport metric, mobility, must be reevaluated.


One of the most widely used metrics for describing the quality of carrier transport through a semiconductor is mobility (μ). Initially defined as the constant of proportionality between carrier velocity and the electric field across a material, μ has often been considered an intrinsic indicator of semiconductor quality and even quoted in textbook tables. Though it is understood that μ depends on other factors such as doping density and temperature, it has nevertheless been taken as the most important parameter for semiconductor consideration. In fact, consideration of channel materials other than silicon (which suffers from a relatively low μ compared with other bulk semiconductors) for high-performance transistors has largely focused on semiconductors with higher mobility, eventually leading to the classification “high-mobility semiconductors” (usually germanium or III-V compound semiconductors, such as GaAs, which despite higher mobility have other issues in achieving high levels of integration).

For the first 50 years of Moore’s law, using mobility as a key parameter to indicate the quality of a semiconductor for transistors made sense. Channel lengths were long enough to yield an average transport length between scattering events (mean free path) or time between scattering events (mean free time τ) and, thus, a certain mobility: μ = qτ/me (here, q is elementary charge of an electron). What happens if the channel length falls below the average length between scattering events, or, in the most extreme case, what happens if the channel is ballistic? As shown in Fig. 5, the use of mobility in such a short-channel transistor is misleading, as it no longer accurately indicates the quality of carrier transport through the semiconducting channel.

Fig. 5 Is mobility meaningful for all transistors?

(A) Generic schematic of a long-channel transistor with a corresponding energy band diagram illustrating how the scattering events (red) of electrons (green) moving across the channel lead to a potential drop (sloped bands) of the applied drain-source field (qVds) and, hence, a substantial resistance in the channel (Rch) compared with resistance at the contacts (Rc). Ec, conduction band edge; Ev, valence band edge. (B) Same as (A), but for a short-channel transistor where there are very few scattering events in the channel (quasi-ballistic) and hence the potential is dropped at, and the device is limited by, the contacts. (C) Conceptual transfer curves for the two devices, showing how mobility (μ) mistakenly suggests better performance in the long channel. This diagram illustrates why mobility is no longer a meaningful metric for short-channel (high-performance) transistors but is still valid in long-channel (thin-film) transistors. I, current; V, voltage; Id, drain current.

With performance in short-channel transistors being determined almost exclusively by the injection of carriers at the source-drain contacts, extraction of mobility from device data defies the actual meaning of the parameter. The example in Fig. 5 illustrates how the band structure and relevant resistances change between long- and short-channel transistors. Extraction of mobility from two such transistors could yield μ that is an order of magnitude smaller for the short-channel devices, even though the performance is much better. This is a fallout of the widely used field-effect mobility expression, wherein μ = gmLch/(WCVds) (here, W is the device width, C is the capacitance, and Vds is the drain-source voltage), where the transconductance (gm) goes up but not nearly as much as Lch goes down when scaling from long to short channels (all other terms remain the same). The contacts, including Rc, are identical in the two devices, as is the applied voltage, but the extraction of mobility from the device data relies on the assumption that transport is limited by the scattering in the channel, as in the long-channel case.

In reality, mobility is no longer meaningful for high-performance transistors (all of which are of the short-channel variety), regardless of whether they have silicon, III-V materials, or nanomaterial channels. The saturation velocity of carriers will matter, as will the effective mass, for determining how well carriers move through the channel. Consider the difference in common expressions for current in a long-channel (traditional) MOSFET (91)Embedded Imageversus a 1D short-channel nanomaterial transistor (92)Embedded ImageIn addition to voltage dependencies [gate-source voltage (Vgs), threshold voltage (Vt), and Vds], current in the long-channel transistor depends on mobility, gate capacitance (Cox), and spatial parameters (W and Lch). In contrast, the short-channel nanomaterial transistor shares none of these dependencies. Rather, the current for the 1D nanomaterial transistor relies on the Fermi function [f (indicates electron distribution)]; carrier velocity (v); transmission probability (Tp), including the probability that carriers will make it through the metal-nanomaterial contact without scattering; and density of energy states (D), with respect to energy (E) and temperature (T). The only material consideration in the long-channel expression is μ, whereas the short-channel transistor accounts for D, v, and f, as these are the material-related parameters that become relevant when scattering in the channel is minimal. Hence, at this point of development, relying on mobility as a metric when discussing options for high-performance transistors causes confusion and distraction from the parameters that matter most. This is especially true for nanomaterials, for which reports of mediocre mobilities extracted from short-channel transistors undercut the actual potential of the material. Mobility remains a useful parameter for comparing TFTs, as they are long-channel devices.

Thin-film transistors

There are many applications for which a digital transistor switch is needed without the extreme performance requirements of computational devices. This became especially clear in the 1980s, when a revolution was beginning to stir in display technology with the need for a more compact, mobile display for laptops. Liquid crystal displays were favored but needed transistors for the backplane to drive the pixels. In 1981, researchers showed that a-Si provided the answer—it could be deposited onto glass substrates, was mostly stable, and had sufficient mobility (0.1 to 1 cm2 V−1 s−1) to yield the necessary level of drive current (Ion). The size of the a-Si TFTs did not have to be small, as the typical pixel is on the order of 100 μm by 100 μm, and the TFTs needed to be large to provide the required Ion. Perhaps most importantly, the a-Si TFTs could be fabricated on large substrates at relatively low cost.

With a-Si TFTs, the display revolution began. Shortcomings, including bias-stress instability (change in the voltage needed to turn the TFT on after prolonged operation) and low mobility, led to development of other TFT options, including polysilicon (μ ~ 100 cm2 V−1 s−1) (4). Although too costly for replacing a-Si in the backplane, polysilicon has become important for display driver circuits in mobile applications, as it is still considerably cheaper than using high-performance MOSFETs. Much effort was devoted to using polysilicon to drive organic light-emitting diode (OLED) displays, which require much higher drive currents than a-Si TFTs could ever deliver, but the nonuniformity in threshold voltage in the polysilicon TFTs gave concern for causing nonuniformity in display brightness (5). The latest advancement has been the use of metal oxide materials—in particular, InGaZnO (IGZO), which offers manufacturing costs on par with a-Si, mobility near that of polysilicon, and better stability. IGZO TFTs now drive the latest OLED displays on the market, yet they have their own limits based on processing temperature and mobility pegged at ~100 cm2 V−1 s−1 for reasonable synthesis temperatures.

Nanomaterials hold much promise for TFTs. Even though being formed into an inhomogeneous thin film seems to belie the advantages of the nanomaterials, they still are shown to deliver superb performance and processing benefits. For example, CNTs that are simply drop cast from solution onto a substrate to form a thin film (the cheapest fabrication approach possible, as it is amenable for printing processes) consistently deliver mobilities of 10 to 100 cm2 V−1 s−1 (6971, 9395). Further efforts to induce alignment in the CNT thin films could boost mobility much higher than 100 cm2 V−1 s−1 (68), which would be revolutionary performance improvement for TFTs processed in solution phase. TMDs have also shown encouraging performance in thin films, with mobilities of 1 to 40 cm2 V−1 s−1 (96100), but they remain limited by insufficient synthesis to fabricate large numbers of transistors on a single substrate and the required use of high-temperature synthesis (not processed in solution). With cost being one of the most important driving factors for TFT applications, the most promising nanomaterial options are those that help break the cost barrier of current technologies. The most attractive way for this to happen is for a TFT to be printed rather processed in a vacuum or at a high temperature. This strength is beginning to receive attention for nanomaterial TFTs (101106).

There are many other applications that benefit from current and future TFT technologies. Displays are presently the largest, and thus the most emphasized, but gas and biological sensors, optical detectors, radio-frequency identification tags, and Internet-of-Things applications also abound. Advancements in TFTs that allow for performance improvement and cost reduction are needed to open the way for a myriad of such exciting applications. Nanomaterials are poised to provide such solutions, requiring further improvement in synthesis and thin-film formation; discovery of better contact interfaces; and realization of stable, consistent TFT operation.

New generation of transistors

Thus far, the focus of this Review has been how nanomaterial transistors have the potential to provide transformative solutions in high-performance and thin-film applications. Yet there are other, completely new and distinct application spaces for which nanomaterial transistors are particularly suited. Just as TFT research is focused more on cost than performance, studies of these new generations of transistors focus on other opportunities, such as optical transparency or biocompatibility. A subset of new-generation transistor applications— including printed electronics (103), flexible electronics (93), transparent electronics (40), and biomedical electronics (107)—is depicted in Fig. 6. In addition to these areas (though not specifically highlighted here), nanomaterial transistors are beneficial in harsh environments [high temperature or radiation (108, 109)] such as space or medical imaging applications, where the thinness and small cross-sectional area are among several nanomaterial advantages enabling greater protection from device damage.

Fig. 6 New application spaces for nanomaterial transistors.

(A) Printed electronics, where nanomaterials offer air-stable metallic, semiconducting, and even insulating options for the low-cost fabrication of multifunctional electronics. [From (110)] (B) Flexible electronics. Many demonstrations of nanomaterial transistors on flexible substrates have shown their robustness to mechanical deformation. [Modified from (93), with permission] (C) Transparent electronics can benefit greatly from the near complete optical transparency of nanomaterials. [From (111)] (D) Biomedical electronics require materials that can be safely dissolved on skin or even in vivo, and nanomaterials show promise for yielding the necessary function at quantities small enough to be safe. [Modified from (107), with permission]

The field of printed electronics has grown dramatically over the past 20 years. Relying almost exclusively on organic polymer materials, applications of printed electronics have been quite limited. Nanomaterials have the potential to offer conducting, semiconducting, and insulating printable inks that are compatible, stable, and able to be modulated for specific application needs. Such a toolkit of inks would be groundbreaking for this field that has potential to revolutionize on-the-fly electronics in an analogous fashion to how 3D printing of mechanical structures has transformed prototyping.

Nanomaterials offer some of the most promising possibilities for electronics that are flexible, transparent, or both. In addition to their substrate independence (discussed above), the atomic thinness of the nanomaterials also renders them nearly 100% transparent to visible light and has been exploited in some demonstrated all-2D transistors (40, 43), motivated by the ability to create completely transparent circuits. Furthermore, the electronic properties of nanomaterials have proven to be robust to mechanical deformation for flexible substrate applications.

Finally, biomedical applications that have requirements of biocompatibility could also benefit from nanomaterials (107). For in vivo applications, small quantities of nanomaterials could be sufficiently safe to enable diagnostic circuits. Electronics applied directly to the skin are another possibility, where nanomaterials would mostly provide the types of benefits outlined in the flexible electronics discussion above.


Transistors have completely transformed our daily lives, in areas ranging from communication to computation to comfort. As the limits of silicon transistors are unavoidably upon us, an intensified consideration of other transistor options is imperative. It is also important to keep clear the relevant deliverables for certain transistor applications spaces: namely, high performance and thin film. High-performance transistors are used in all computational devices, from servers to smartphones, whereas TFTs primarily provide the backplane circuitry for displays. The meaningfulness of parameters such as mobility must be kept in context for the different transistor applications so that scientific advances can be kept in proper perspective.

Nanomaterials, including carbon nanotubes and TMDs, show great promise for both high-performance transistors and TFTs. Not every scientific discovery or advancement benefits both nanomaterial high-performance transistors and TFTs, yet many reports confuse this fact. What is clear from the thousands of demonstrated nanomaterial transistors is that they offer considerable advantages, promoting transformative advancement in high-performance, thin-film, and completely new application spaces. Comparison of the distinctive aspects of the different nanomaterial options, or the transistors assembled from them, suggests greater suitability of certain nanomaterials for particular applications (e.g., the instability of most X-enes in air largely precludes their use in low-cost, thin-film processing).

Going forward, much work remains in terms of improving the synthesis and resultant uniformity of nanomaterials, positioning them onto target device substrates, understanding and optimizing key interfaces (contacts and gate), and exploring re-invented transistor structures that make more direct use of the nanomaterial benefits. Varied levels of progress have been achieved in addressing these challenges for each nanomaterial, but each requires further attention to be suitable for a transistor technology. The most accessible area in the near term is the use of nanomaterials for printed (low-cost) TFTs, where they are already beginning to show consistent advantages over existing technologies.

Perhaps the greatest challenge to this unprecedentedly large research field of nanomaterial transistors is to make appropriate use of the deluge of scientific and engineering advancements. Hopefully, in the years to come, more collaborative and comprehensive advancements will be published that not only demonstrate a singular breakthrough on one of the challenges for nanomaterials but also give thorough evidence of the impacts of their solution on other key deliverables for a certain nanomaterial transistor application. With sufficient continued research investment into exploring nanomaterial transistors, there is little doubt that 50 years from now the next generation of scientists will be reflecting on a full century of Moore’s law, in one form or another.


  1. There is no longer much meaning behind this dimensional indicator for a certain technology node, as discussed in, where it is noted that the 14-nm node has 35-nm-long channel lengths with 8-nm-wide silicon fins.
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