Report

Carbon nanotube transistors scaled to a 40-nanometer footprint

See allHide authors and affiliations

Science  30 Jun 2017:
Vol. 356, Issue 6345, pp. 1369-1372
DOI: 10.1126/science.aan2476

You are currently viewing the abstract.

View Full Text

Carbon nanotubes on the roadmap

The formal challenge for high-performance transistors is to fit within ever smaller devices. They need to shrink from a lateral dimension of about 100 to 40 nanometers. Cao et al. fabricated tiny devices by using a single semiconducting carbon nanotubes, as well as arrays of these nanotubes. High performance (a high saturation on-state current >1.2 milliamperes per micrometer and a conductance >2 millisiemens per micrometer) was delivered by making end-bonded contacts to the nanotubes with cobalt-molybdenum alloys.

Science, this issue p. 1369

Abstract

The International Technology Roadmap for Semiconductors challenges the device research community to reduce the transistor footprint containing all components to 40 nanometers within the next decade. We report on a p-channel transistor scaled to such an extremely small dimension. Built on one semiconducting carbon nanotube, it occupies less than half the space of leading silicon technologies, while delivering a significantly higher pitch-normalized current density—above 0.9 milliampere per micrometer at a low supply voltage of 0.5 volts with a subthreshold swing of 85 millivolts per decade. Furthermore, we show transistors with the same small footprint built on actual high-density arrays of such nanotubes that deliver higher current than that of the best-competing silicon devices under the same overdrive, without any normalization. We achieve this using low-resistance end-bonded contacts, a high-purity semiconducting carbon nanotube source, and self-assembly to pack nanotubes into full surface-coverage aligned arrays.

View Full Text