Physical Structure and Inversion Charge at a Semiconductor Interface with a Crystalline Oxide

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Science  20 Jul 2001:
Vol. 293, Issue 5529, pp. 468-471
DOI: 10.1126/science.293.5529.468


We show that the physical and electrical structure and hence the inversion charge for crystalline oxides on semiconductors can be understood and systematically manipulated at the atomic level. Heterojunction band offset and alignment are adjusted by atomic-level structural and chemical changes, resulting in the demonstration of an electrical interface between a polar oxide and a semiconductor free of interface charge. In a broader sense, we take the metal oxide semiconductor device to a new and prominent position in the solid-state electronics timeline. It can now be extensively developed using an entirely new physical system: the crystalline oxides–on–semiconductors interface.

Inversion charge associated with field-effect phenomena at oxide/semiconductor interfaces can be described using Maxwell's first equation ∇ · D = ρ, where D is the dielectric displacement in the oxide and ρ is the inversion charge in the semiconductor. Our understanding of the electrostatics of field-effect phenomena deduced from this expression relies on the assumption that dielectric displacement is continuous at the oxide/semiconductor interface. This assumption, with its application in SiO2/Si capacitors (1), is the foundation of essentially all of modern metal oxide semiconductor (MOS) device physics. Because alternative materials are being considered as replacements for the amorphous SiO2 dielectric on silicon, however, and particularly because attempts to add higher functionality to a silicon platform are being made, we would do well to reconsider how physical structure at oxide/semiconductor interfaces couples to inversion charge.

Much of the effort expended to date in the search for an alternative to SiO2 has focused on amorphous oxides, attempting to extend the SiO2/Si concept. Although this approach is attractive, defects at an amorphous/crystalline interface associated with steric hindrance and bond coordination (2,3) can lead to a discontinuity in dielectric displacement. Maintaining continuity in dielectric displacement via passivation of these defects with hydrogen is a convenience that works for SiO2/Si, but it is a methodology that is not universally applicable. Steric hindrance and the statistical nature of defect formation with directional bonding are intrinsic to an amorphous/crystalline boundary, but these defects can be avoided entirely with a crystalline structure at a polar oxide/semiconductor interface (4).

Here we consider crystalline oxides on semiconductors (COS) as candidate solutions to the alternative gate dielectrics problem and suggest their much broader potential for new functionality in solid-state electronics. Our thesis is that the physical structure at a COS interface can be made perfectly commensurate, and that in such a state, the systematics of crystalline periodicity lead to an unprecedented ability to manipulate dielectric displacement and inversion charge at a dielectric/semiconductor surface. This notion thus has implications for entirely new device physics and a device functionality that cannot even be considered with SiO2 on silicon.

Looking at the physical structure of COS, a three-panel construction of Z-contrast images is shown (Fig. 1) of Ba0.725Sr0.275O and SrTiO3on pure silicon and of BaTiO3 on pure germanium, all grown using molecular beam epitaxy (MBE) techniques. The Ba-Sr-O compound (Fig. 1A) has a 5-eV band gap (5) and is alloyed to match the lattice parameter of the (001) face of silicon. The overlay in the left side of the image shows a simple model of the epitaxial cube-on-cube NaCl-type oxide structure of the alkaline earth oxide on silicon. Although the oxygen atoms are not imaged, the bright contrast of the heavy alkaline earth metal atoms and the [110] symmetry of the epitaxial structure are clear. The case in which SrTiO3 has been grown and strained 2% to be commensurate to silicon is illustrated in Fig. 1B, and BaTiO3 on germanium with its room-temperature lattice match is shown in Fig. 1C.

Figure 1

Alkaline earth and perovskite oxide heteroepitaxy on silicon and germanium. The figure illustrates our ability to manipulate interface structure at the atomic level using our (AO)n(A′BO3)mstructure series. The n/m ratio defines the electrical characteristics of this new physical system of COS in a MOS capacitor. In (A), n = 3, m= 0; in (B), n = 1, m = 2; in (C), n = 0, m = 3.

These lattice images are members of a COS structure series that can be generically written as (AO)n(A′BO3)m. The subscripts n and m in this structure series are integer repeats of atomic planes and unit cells of constituent crystalline layers. Although this structure series can be quite broadly applied, we will discuss it here for cases where A and A′ are elements or combination of elements out of group IIA of the periodic table (that is, Ba, Sr, Ca, and Mg) and B is a group IVA transition metal such as Ti or Zr.

In analogy to III-V gallium arsenide alloy heteroepitaxy (6), our oxide MBE synthesis technique (4, 7, 8) has shown that lattice-matched oxides can be formed in our structure series by source shuttering. (AO)n- (A′BO3)m can be adapted to germanium (Fig. 1C) and thus to silicon-germanium heterojunction technology to provide a flexible platform for alternative gate applications and for new functionality. A collection of lattice parameters and their temperature-dependent changes has been assembled for silicon and germanium and three perovskite oxides (9). The room-temperature cubic lattice parameter of the semiconductor alloy series from pure silicon to pure germanium varies from 5.43 to 5.65 Å. The perovskites CaTiO3, SrTiO3, and BaTiO3 are simple cubic “2-4” perovskite structures, in which the 2+ alkaline earth metal ions occupy the cube corners and the 4+ transition metal is in the center of the cube, octahedrally coordinated with oxygen ions in the face-centered sites of the unit cell (10). These three perovskites are mutually soluble in each other. By mixing Ca and Sr, for instance, in a 60/40 ratio, the 5.43 Å lattice parameter of pure silicon can be obtained at room temperature, because the perovskites rotate 45° so that the [100] direction in the oxide is parallel with [110] Si and its 3.84 Å spacing (11). The lattice parameters of two pure perovskites are of particular note: Pure BaTiO3 matches the 5.65 Å lattice parameter of pure germanium at room temperature, and pure CaTiO3 matches the 5.44 Å lattice parameter of pure silicon at 515°C; no alloying is required for either of these perovskites for growth on the two end members of a Si-Ge substrate series. Results for BaTiO3 on germanium are discussed below.

A Z-contrast image is shown (Fig. 1C) of the epitaxy and structural perfection obtained when pure BaTiO3 is grown on pure germanium using the precepts of layer-by-layer energy minimization developed in (12), and is the ferroelectric BaTiO3/Ge structure that was envisioned by the Bell group in 1957 (13, 14). In this early work, the researchers looked for dielectric displacement to alter the surface charge set up by ferroelectric polarization in a thin BaTiO3 crystal, glued to the surface of germanium. These notions of coupling ferroelectric polarization from a crystalline oxide with the field effect in a semiconductor were clearly fundamental in their insight: These were expectations for entirely new device physics. The “glue” is now a layered heteroepitaxial structure that is thermodynamically stable and is commensurate at the atomic level. Experimental evidence presented below suggests that this BaTiO3/Ge structure may well be electrically perfect. It completely avoids the trapped charge that induced the discontinuity in dielectric displacement and inversion charge that hampered its early implementation.

COS offer us an interface physics approach to the development of new gate dielectrics for transistor technology through epitaxial growth of the oxides. Moreover, this heteroepitaxial approach allows us to systematically manipulate interface band structure as well as interface charge by layer-sequencing the structure. Although our interest here is to demonstrate the broad utility of COS and their device physics implications, we first demonstrate that the high field mobility (the interface scattering regime) in a simple COS-based field-effect transistor (FET) rivals values obtainable in SiO2-based devices (15). In the plot ofn-channel mobility versus field data for a 50-μm channel-length FET (Fig. 2) (16), the COS dielectric is a heterojunction of SrTiO3 with two monolayers of Ba0.75Sr0.25O at the interface with silicon. This structure is (AO)n(A′BO3)m, with n = 2 and m = 52. The peak mobility that we extract from this n-channel FET, 321 cm2/V · s, is the highest mobility value that has been reported for any alternative gate FET (17–19). Additionally, the field dependence is such that at high fields where interface scattering dominates, the mobility approaches what is obtainable with state-of-the-art SiO2/Si.

Figure 2

The n-channel mobility as a function of field evaluated self-consistently with 8.6 femto farads (fF)/μm2 as the gate capacitance in a 210 Å film. SiO2/Si values are (A) H2 processed,D it = 3 × 1010/cm2-eV (17); (B) H2 processed, D it = 3 × 1011/cm2-eV; and (C) dry-oxidized with D it = 1 × 1013/cm2-eV. The data (D) for SrTiO3/Si were determined with the Pao-Sah model (15) andI ds-V gs data at 50 mVV ds. I ds, source-drain current; V ds, source-drain voltage;V gs, gate-to-substrate voltage; E, the electric in the transistor channel, normal to the gate.

We have done no transistor process optimization for this device, nor have we attempted to optimize strain effects (the SrTiO3 is 2% mismatched to silicon). The field dependence and magnitude of the mobility that we obtain with this device can be explained by fluctuations in inversion charge at the interface (15), which indeed is the case for curve C (dry-oxidized SiO2), and by strain in the silicon. Epitaxial strain associated with the 2% lattice mismatch between SrTiO3 and silicon induces misfit dislocations that in turn lead to local variations in the silicon band gap and spatial fluctuation of the inversion charge (20). Although the data in Fig. 2 provide critical information about channel mobility and scattering phenomena, these transport measurements are a reflection of band-gap energy for a very limited range of silicon surface potential. Our experiments have substantially broadened the surface potential variation over which interface electrostatics and device physics implications are addressed for the COS system. We rely on experimental data obtained from MOS capacitors (21) that give us a much broader range of surface potential variation, taking the semiconductor surface from accumulation through depletion and into inversion, as opposed to surface inversion in the transistor data inFig. 2.

The surface potential, interface charge, and inversion charge in the semiconductor of the MOS capacitor are all functions of bias voltage and frequency. MOS capacitor function requires that the oxide dielectric act as a Schottky barrier with no free charge and support the dielectric displacement that sets up inversion charge in the underlying semiconductor. This coupling of dielectric displacement to inversion charge is critically dependent on the details of the interface band structure of the MOS capacitor.

Recent treatments of this problem for a number of candidate oxides being considered as alternative dielectrics on silicon (22, 23) have predicted that although a number of the oxides in the perovskite class have the desired high dielectric constants, band offset and alignment are highly unfavorable; namely, the barrier height to electron transfer across a perovskite dielectric on silicon can be small or even nonexistent. A recent spectroscopic study of the SrTiO3/Si interface (24) has confirmed that band offset is indeed a problem for perovskites on silicon.

Table 1 gives theoretical values for valence band (VB) and conduction band (CB) offsets for SrTiO3 (25), and the corresponding distinctions estimated here for the alkaline earth oxide BaO. SrTiO3 (as is typical of the simple perovskites SrTiO3, CaTiO3, and BaTiO3) in a p-channel FET on germanium or silicon would have positive values for VB. However, CB is only slightly positive for germanium and is negative for silicon; an n-channel FET would not switch.

Table 1

Valence and conduction band offset parameters for COS structures on silicon and germanium.

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This asymmetry in band structure is attributable to the fact that the band gap for transition metal perovskites lies between the valence band of filled oxygen 2p states and the conduction band of empty transition metal d states. The weighting of the transition metal d states that the integrated charge neutrality level (CNL) drives is thus responsible for the asymmetry. Measurements of SrTiO3 on silicon reporting CB values between 0.0 and 0.1 ± 0.1 eV, but VB values in excess of 2 eV (24) confirm this scenario. This band offset asymmetry could thus be fatal, but it is here that the physics base for the COS approach to the design of transistor gate dielectrics can be clearly illustrated.

Our COS structure series, (AO)n(A′BO3)m, allows the band structure to be systematically manipulated. Unlike the transition metal perovskites, the alkaline earth oxides such as BaO are strongly ionic and the CNL is in the middle of the band gap. We have estimated the entries in Table 1 for BaO assuming the mid-gap CNL and clearly show that band offsets, both CB and VB, are substantially positive for germanium and for silicon. Therefore, if two or more BaO planes were inserted between a perovskite and germanium or silicon, then the asymmetry of the band structure would, according to the numbers in Table 1, adjust and support dielectric displacement across the junction. This is a simple and striking prediction for our heteroepitaxial approach.

A collection of leakage current data obtained for BaTiO3 on germanium is presented (Fig. 3) with two values of the AO repeat,n = 1 and n = 6. The open circles show the n = 1 data for BaTiO3 directly on germanium, with the BaTiO3 layer being 250 Å thick (Fig. 1C). Although this heteroepitaxial structure is perfectly commensurate and bulk BaTiO3 has a band gap of 3.4 eV (5), a BaTiO3 thin film grown directly on germanium is not an effective barrier to electron transfer. However, if as few as six atomic planes of BaO are grown on germanium first, then the leakage current (open squares) drops by six orders of magnitude. We are investigating the n/m dependence of these observations by studying the photoelectron spectra for these structures when the BaTiO3 film is only a few unit cells thick (25). Our preliminary results show a valence band offset of 2.8 eV and a conduction band offset of 0.05 eV for n = 1 andm = 2. Collectively, these data offer dramatic evidence for the physical structure dominance of the electrical structure in our heteroepitaxial oxide series. Within the context of the generality of our structure series and its n/m configurations, interface band structure can be adjusted for many of the perovskite and transition metal oxides analyzed (23).

Figure 3

Leakage current data for (AO)n(A′BO3)mon germanium. The data are plotted as absolute values of leakage current.

We turn now to the final part of our discussion of the electrical structure of COS dielectrics. Interface charge is recognized as a substantial problem for field-effect charge inversion in a transistor. Interface charge can completely screen the semiconductor from an applied field and even result in a discontinuity in dielectric displacement, as was the case for the ferroelectric field of BaTiO3 crystals glued to germanium (13,14). The thesis of our heteroepitaxial approach is that oxide dielectrics can be grown as monolithic single-crystal structures on semiconductors, tying up the dangling bonds that are typical of the amorphous SiO2/Si structure. This would in turn eliminate extrinsic interface charge and maintain continuity in dielectric displacement at the oxide/semiconductor interface. We used capacitance data (Fig. 4) to prove this point.

Figure 4

(A and B) High-frequency–low-frequency capacitance data for BaTiO3/Ge. Data were taken with aluminum top and bottom electrodes. The doping is p type, 1017/cm3. The measured flatband voltage is –0.8 volts. With an interface state density of 1010/cm2, the flatband shift indicates a fixed positive charge of 1012/cm2.C/A, specific capacitance;V g, gate voltage; φ, surface potential of the semiconductor; φf, surface potential at the femi level.

High-frequency (HF, 1 MHz) and low-frequency (LF, 10 Hz) capacitance data were taken from a 250 Å–thick BaTiO3film on p-type germanium (Fig. 4A). An expanded view of the data in the bias range where the germanium surface potential varies from zero to its value at the Fermi level is shown (Fig. 4B). We can extract the density of interface charge (our measure of interface perfection) from ΔC,C LF – C HF in this bias range (21).

The capacitance of the MOS capacitor can be broken down into its component parts C ox andC Ge, as identified in the equivalent circuit inset in Fig. 4A (C ox is the specific capacitance of the BaT:O3 film). C Geis dependent on the germanium surface potential, interface defect charge, and inversion charge. The hashed regions are the bias range where the field effect is “depleting” the oxide semiconductor interface of majority carrier charge and initiating the process of minority carrier charge inversion (the upward turn ofC LF in Fig. 4A is the signature of field-effect–driven electron-hole pair generation and charge carrier inversion in the underlying p-type germanium). Dielectric displacement via gate charge must overcome the screening effect of any interface-trapped charge before the germanium inversion charge can even respond. ΔC in this depletion region provides a measure of any extra capacitance that might be associated with the charging dynamics of interface traps.

The electron-hole recombination rate in this depletion region is frequency-dependent, as is the rate at which electrons can move into and out of interface traps. The majority carrier electron-hole contribution to CGe can keep up at high frequencies, but electron trapping at the interface cannot. Therefore, by sweeping the frequency (ω) of the small signal ac gate voltage,dV g(ω), the capacitance associated with interface trapped charge, C it(ω), goes to zero as ω ⇒ ∞. the contribution of interface charge can be separated.

The data for the determination of the interface trap density, D it, are provided (Fig. 4B);D it ∝ ΔC. As these data show, ΔC and hence trapped charge for our commensurate interface are negligible. D it is indistinguishable from zero through the entire depletion region. We therefore observe aD it value of <1010/cm2-eV; to our measurement sensitivity, this is an electrically perfect interface. The flat band shift indicates a fixed positive oxide charge of 1012/cm2: a value consistent with an error of 50 parts per million in the Ba/Ti ratio in the structure. Germanium inverts from its majority carrier p-type behavior to minority n-type behavior over a narrow 1-V range. A ferroelectric hysteresis is not detectable in the capacitance-voltage data, because the coercive field for BaTiO3 is only 500 V/cm (26): This value of the coercive field would shift the flat band by less than 1 mV in this 250 Å film.

To our knowledge, this is the first demonstration of field-effect charge inversion for a gate oxide on germanium. Its basis is the generalization of our structure series (AO)n(A′BO3)mand the atomic-level flexibility that this structure series gives us to manipulate physical and electrical structure in a MOS capacitor. The COS approach enables the formation of commensurate interface structures while maintaining continuity in dielectric displacement and systematic control of inversion charge. COS in a MOS device is applicable to silicon or germanium and to any silicon-germanium alloy. Moreover, it offers promise in support of emerging technologies such as ferroelectric lithography (27) and quantum computing (28, 29), in which interface defect charge must be controlled to values less than 1010/cm2 .


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