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Logic Gates and Computation from Assembled Nanowire Building Blocks

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Science  09 Nov 2001:
Vol. 294, Issue 5545, pp. 1313-1317
DOI: 10.1126/science.1066192

Abstract

Miniaturization in electronics through improvements in established “top-down” fabrication techniques is approaching the point where fundamental issues are expected to limit the dramatic increases in computing seen over the past several decades. Here we report a “bottom-up” approach in which functional device elements and element arrays have been assembled from solution through the use of electronically well-defined semiconductor nanowire building blocks. We show that crossed nanowire p-n junctions and junction arrays can be assembled in over 95% yield with controllable electrical characteristics, and in addition, that these junctions can be used to create integrated nanoscale field-effect transistor arrays with nanowires as both the conducting channel and gate electrode. Nanowire junction arrays have been configured as key OR, AND, and NOR logic-gate structures with substantial gain and have been used to implement basic computation.

Fundamental physical constraints and economics are expected to limit continued miniaturization in electronics by conventional top-down manufacturing during the next one to two decades (1,2) and have thus motivated efforts world wide to search for new strategies to meet expected computing demands of the future. Bottom-up approaches to nanoelectronics (2), where the functional electronic structures are assembled from well-defined nanoscale building blocks, such as carbon nanotubes (3–8), molecules (9–11), and/or semiconductor nanowires (12–14), have the potential to go far beyond the limits of top-down manufacturing. For example, single-walled carbon nanotubes (NTs) have been used as building blocks to fabricate room-temperature field-effect transistors (FETs) (3–5), diodes (6,7) and recently, an inverter (8), which represents a key component for logic. However, the inability to control whether NTs are semiconducting or metallic (2, 5) makes specific device fabrication largely a random event and poses a serious issue for integration beyond the single–device element level. A potential solution to the problem of coexisting metallic and semiconducting NTs involves selective destruction of metallic tubes (5), although such an approach requires extensive top-down lithography and subsequent processing to implement.

Semiconductor nanowires (NWs) have also been used as building blocks for assembling a range of nanodevices including FETs (12,13), p-n diodes (13, 14), bipolar junction transistors, and complementary inverters (14). In contrast to NTs, these NW devices can be assembled in a predictable manner because the electronic properties and sizes of the NWs can be precisely controlled during synthesis (12–15) and methods exist for their parallel assembly (16). However, previous NW and NT single device elements represent only an initial step toward nanoelectronic systems, which will require both the formation of device elements and integrated device arrays in high yield. To this end, we report assembly of p-type silicon (p-Si) and n-type gallium nitride (n-GaN) NWs to form crossed nanoscale p-n junctions and junction arrays in which the electronic properties and function are controlled in a predictable manner to provide both diode and FET elements in high yield. Importantly, nanoscale p-n junction and FET arrays have been configured as OR, AND, and NOR logic gates with substantial gain, and these gates have been interconnected to demonstrate computation with a half-adder. Our approach leads naturally through the bottom-up paradigm to integration at the nanoscale and represents a step toward the creation of sophisticated nanoelectronics.

The single-crystal p-Si and n-GaN NWs used in this study were synthesized by nanocluster-catalyzed methods described previously (14, 15, 17, 18) and had diameters of 10 to 25 and 10 to 30 nm, respectively, although NWs as small as 2 nm can be prepared (15). These NWs were chosen for our studies because the oxide coating on their surfaces can be independently varied (18) to enable good control of junction electronic properties. To demonstrate this feature, which is critical for assembly of more complex integrated devices, we have assembled and characterized the electronic properties of a large number of crossed p-Si/n-GaN junctions (18) (Fig. 1). Current-voltage (I-V) measurements show that the p-Si/n-GaN crossed NW devices exhibit current rectification characteristic of p-n diodes with a typical turn-on voltage of about 1.0 V (Fig. 1A) (19). These results are highly reproducible: Current rectification was observed in over 95% of the more than 70 crossed p-n NW devices studied, and in addition, 85% of the devices exhibited low turn-on voltages between 0.6 and 1.3 V (Fig. 1A, top left inset). The reproducible assembly of crossed NW structures with predictable electrical properties contrasts sharply with results from NT-based devices and has enabled us also to explore the assembly and properties of integrated p-n junction arrays. Importantly, electrical transport measurements made on a typical 4 by 1 crossed p-Si/n-GaN junction array (Fig. 1B) show that the four nanoscale cross points form independently addressable p-n junctions with clear current rectification and similar turn-on voltages. These data demonstrate the high yield and reproducibility of our crossed NW p-n devices and represent an important and necessary step for the rational assembly of more complex devices such as logic gates (see below).

Figure 1

Crossed NW nanodevice elements. (A) Turn-on voltage distribution for crossed NW junctions. The green cross-hatched area indicates the range for low turn-on voltage junctions formed from as-assembled NW junctions, and the red cross-hatched area indicates high turn-on voltage devices after local oxidation of the junction. (Top left inset) Histogram of turn-on voltage for over 70 as-assembled junctions showing a narrow distribution around 1 V. The high turn-on voltage devices have a broad distribution but generally fall into the range of 5 to 10 V. (Top right inset) An example of an I-Vresponse for low (green) and high (red) turn-on voltage elements. The red curve is multiplied by 1000 for better viewing. The inset inside the top right inset shows a typical scanning electron micrograph (SEM) of a crossed NW device. Bar: 1 μm. (B)I-V behavior for a 4(p) by 1(n) multiple junction array. The four curves represent the I-Vresponse for each of the four junctions and highlight reproducibility of assembled device elements. (Inset) An example of a multiple crossed NW device. Bar: 2 μm. (C) Gate-dependentI-V characteristics of a crossed NW-FET. The NW gate voltage for each I-V curve is indicated (0, 1, 2, and 3 V). (Top left inset) The red and blue curves show I versus V gate for n-NW (red) and global back (blue) gates when the bias is set at 1 V. The transconductance for this device was 80 and 280 nS (V sd= 1 V) when using the global back gate and NW gate, respectively. (Bottom right inset) The measurement configuration.

In addition to these low turn-on voltage diodes, high turn-on voltage p-n junctions can be used as nanoscale FETs (Fig. 1C). Specifically, a p-channel FET with both a nanoscale conducting channel and a nanoscale gate is formed from a n-GaN/p-Si crossed NW structure; we refer to these structures as crossed NW FETs (cNW-FETs). The high turn-on voltage junctions required to assemble cNW-FETs were reproducibly formed by increasing the oxide layer thickness at the junctions by either thermal oxidation of the SiNWs (18) or by passing a high current through the junction in the air (20). Transport data recorded on over 50 p-n junctions prepared in this way (Fig. 1A) show that turn-on voltages greater than 5 V can be achieved in nearly quantitative yield, while still maintaining good conduction through individual NWs. The corresponding I-V data recorded on a typical cNW-FET, where the n-GaN NW is used as a nano-gate, exhibit a large decrease in conductance with increasing gate voltage (Fig. 1C) (21). Specifically, the conductance can be changed by a factor of more than 105 with only a 1- to 2-V variation in the nano-gate, whereas the conductance changes by only a factor of 10 when a global back-gate is used (Fig. 1C, top left inset). We attribute the high sensitivity of the cNW-FETs to the intrinsically thin gate dielectric between the crossed NWs, although a complete understanding of this new type of FET will require further investigation. The reproducibility, large gate response, and potential for nanoscale integration make the cNW-FETs attractive for assembling more complex electronic devices in which FETs are critical elements (22). In addition, these characteristics contrast recent work on NTs (3–5, 8) that have used either global back gates, which are incompatible with independent device function, or lithographically defined local gates, which use and are constrained by conventional lithography to obtain nanoscale structures.

The high-yield assembly of crossed NW p-n junctions and cNW-FETs enables the bottom-up approach to be used for formation of more complex and functional electronic devices, such as logic gates. To demonstrate the flexibility of these NW device elements, we have investigated both diode- and FET-based logic (23). First, a two-input OR gate was realized by using a 2(p) by 1(n) crossed p-n junction array with the two p-Si NWs as inputs and the n-GaN NW as the output (Fig. 2A). In this device, the output is low (logic 0) when both input voltages are low (0 V), and the output is high (logic 1) when either or both of the input voltages are high (5 V) (Fig. 2B), where a high input corresponds to forward bias of the corresponding p-n junction. The output-input (V o-V i) voltage response (Fig. 2B, inset) shows that V o increases linearly with V i when one input is set low (0 V), except for the region near 0 V. This low-response region is due to the finite turn-on voltage of the p-n junctions and produces a logic output typically 0.4 to 0.2 V less than the input voltage. Small reductions in V o do not affect the operation of our logic gates because the low turn-on voltage contributions are reproducible and can be readily accounted for in defining the 0 and 1 states. The V o-V i data also show a nearly constant high output when the second input is set high (5 V). The experimental truth table for the 1 by 2 crossed NW device (Fig. 1C) summarizes the input-output response and confirms that this NW device behaves as a logic OR gate. We also note that assembly of more p-n junctions would produce a multiple input OR gate, i.e., a 1 by n junction array for an n-input OR gate.

Figure 2

Nanowire nano-logic gates. (A) Schematics of logic OR gate constructed from a 2 by 1 crossed NW p-n junction. (Insets) An example SEM (bar: 1 μm) of the assembled “OR” gate and symbolic electronic circuit. (B) The output voltage versus the four possible logic address level inputs: (0,0); (0,1); (1,0); (1,1), where logic 0 input is 0 V and logic 1 input is 5 V (same for the below). (Inset) The output-input (V o-V i) relation. The solid and dashed red (blue) lines showV o-V i1 andV o-V i2 when the other input is 0 (1). (C) The experimental truth table for the OR gate. (D) Schematic of logic AND gate constructed from a 1 by 3 crossed NW junction array. (Insets) A typical SEM (bar: 1 μm) of the assembled AND gate and symbolic electronic circuit. (E) The output voltage versus the four possible logic address level inputs. (Inset) The V o-V i, where the solid and dashed red (blue) lines correspond toV o-V i1 andV o-V i2 when the other input is 0 (1). (F) The experimental truth table for the AND gate. (G) Schematic of logic NOR gate constructed from a 1 by 3 crossed NW junction array. (Insets) An example SEM (bar: 1 μm) and symbolic electronic circuit. (H) The output voltage versus the four possible logic address level inputs. (Inset) TheV o-V i relation, where the solid and dashed red (blue) lines correspond toV o-V i1 andV o-V i2 when the other input is 0 (1). The slope of the data shows that device voltage gain is larger than 5. (I) The measured truth table for the NOR gate.

We have also fabricated an AND gate from a 1(p-Si) by 3(n-GaN) multiple junction array (Fig. 2D). In this structure, the p-Si NW is biased at 5 V; two of the GaN NWs are used as inputs, and the third is used a gate with a constant voltage to create a resistor by depleting a portion of the p-Si NW. The logic 0 is observed from this device when either one or both of the inputs are low (Fig. 2E), becauseV i = 0 corresponds to a forward-biased, low-resistance p-n junction that pulls down the output (logic “0”). The logic 1 is observed only when both inputs are high, because this condition corresponds to reverse-biased p-n diodes with resistances much larger than that of the constant resistor, i.e., there is a small voltage drop across the constant resistor and a high voltage is achieved at the output. TheV o-V i data (Fig. 2E, inset) shows constant low V o when the other input is low and nearly linear behavior when the other input is set at high. The truth table for the NW device (Fig. 2F) summarizes the input-output response and confirms that this device functions as a logic AND gate.

In addition, a logic NOR gate was assembled by using a 1(p-Si) by 3(n-GaN) cNW-FET array (Fig. 2G). The NOR gate was configured with 2.5 V applied to one cNW-FET to create a constant resistance of ∼100 megohms, and the p-SiNW channel was biased at 5 V. The two remaining n-GaN NW inputs act as gates for two cNW-FETs in series. In this way, the output depends on the resistance ratio of the two cNW-FETs and the constant resistor. The logic 0 is observed when either one or both of the inputs is high (Fig. 2H). In this case, the transistors are off and have resistances much higher than that of the constant resistor, and thus most of the voltage drops across the transistors. A logic 1 state can only be achieved when both of the transistors are on, i.e., when both inputs are low. TheV o-V i relation (Fig. 2H, inset) shows constant low V o when the other input is high, and a nonlinear response with large change inV o when the other input is set low. Analysis of these data and those from similar structures demonstrates that these two-input NOR gates routinely exhibit gains in excess of five, which is substantially larger than the gain reported for complementary inverters based on Si-NWs (14) and carbon NTs (8). High gain is a critical characteristic of gates because it enables interconnection of arrays of logic gates without signal restoration at each stage (24). The truth table for this NW device (Fig. 2I) summarizes theV o-V i response and demonstrates that the device behaves as a logic NOR gate. Lastly, our multiple-input logic NOR gates can function as NOT gates (simple inverters) by eliminating one of the inputs.

The predictable assembly of logic OR, AND, and NOR (NOT) gates enables the organization of virtually any logic circuit and represents a substantial advance compared with previous studies of NTs and molecular systems. First, the controllable electronic characteristics of the NW building blocks and reproducible properties of the devices assembled from these blocks contrast with the much lower control achieved to date with NTs (3–8). We believe that predictable and reproducible assembly of device elements and arrays is especially important for integration without resorting to extensive top-down lithography to connect to those NT devices that function. Second, the use of crossed NW devices and arrays leads naturally to integration at the nanoscale and should be contrasted with NT (3–5, 8) and molecular (9–11) devices, where the element sizes reported to date (length for NTs and area for molecules) have been determined by the same top-down lithography used in conventional electronics.

Lastly, we have interconnected multiple AND and NOR gates to implement basic computation in the form of an XOR gate (Fig. 3A), which corresponds to the binary logic function SUM, and a half adder (Fig. 3B), which corresponds to the addition of two binary bits. The XOR gate is configured by using the output from AND and NOR gates as the input to a second NOR gate, whereas the logic half adder uses an additional logic AND gate as the CARRY. The truth table for the proposed logic XOR is summarized in Fig. 3C. Importantly, the experimentalV o-V i transport data for the XOR device (Fig. 3, D and E) show (i) that the output is logic state 0 or low when the inputs are both low or high, and logic state 1 or high when one input is low and the other is high; and (ii) that the response is highly nonlinear. The linear response region corresponds to a voltage gain of more than five and is typical of the devices measured to date. This large gain achieved in an XOR configured from CNW-FET NOR gates and a low-gain diode AND gate is due to the high gain of the cNW-FET NOR gates. We believe that further improvements in device performance could be obtained by using cNW-FET elements for all of the logic elements (24). Importantly, the data summarized in the experimental truth table (Fig. 3F) demonstrate that the response is that of the binary logic SUM operation, and thus that we have implemented a basic computation with the NW logic devices.

Figure 3

Nanowire computation. (A) Schematic of logic XOR gate constructed with the output from an AND and a NOR as the input to a second NOR gate. (B) Schematic for logic half adder. (C) Truth table for logic XOR gate. (D) XOR output voltage versus input voltages. The solid and dashed red (blue) lines showV o-V i1 andV o-V i2 when the other input is 0 (1). The slope of theV o-V i data shows that the gain exceeds 10. The XOR gate was achieved by connecting the output electrodes of an AND and NOR gate to two inputs of another NOR gate. (E) The output voltage versus the four possible logic address level inputs for the XOR gate. (F) Experimental truth table for the logic half adder. The logic half adder was obtained by using the XOR gate as the SUM and an AND gate as the CARRY.

Overall, we believe that our predictable and reproducible bench-top assembly of nanoscale crossed p-n diode and cNW-FET elements and arrays, which have enabled the demonstration of all critical logic gates and basic computation, represents an important step toward integrated nanoelectronics built from primarily bottom-up versus top-down approaches. Further improvements can be made by assembling NWs directly onto predefined metal electrode arrays (25) and by creating more highly integrated circuit elements by feeding the output from NW to NW. Implementing these approaches could eliminate the conventional lithography used to wire-up devices in this study. In addition, in a crossbar array with 5-nm diameter NWs, it would be possible to achieve device densities approaching 1012/cm2, which is off the present semiconductor road map for top-down manufacturing. To achieve this goal of bottom-up manufacturing in the future will require substantial work—for example, in developing much greater sophistication in assembly and further improving materials synthesis.

  • * These authors contributed equally to this work.

  • To whom correspondence should be addressed. E-mail: cml{at}cmliris.harvard.edu

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