PerspectiveApplied Physics

Moore's Law Forever?

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Science  10 Jan 2003:
Vol. 299, Issue 5604, pp. 210-211
DOI: 10.1126/science.1079567

When Gordon Moore predicted in 1965 that the number of transistors per integrated circuit chip would continue to double in each technology generation, there were just 30 transistors on a chip. Today, transistor counts—a measure of the capability of an electronic system—exceed a few hundred million for logic chips and even more for memory chips [HN1]. How long can Moore's law continue? [HN2]

The semiconductor industry [HN3] follows Moore's law by shrinking transistor dimensions. But transistors [HN4] cannot be scaled down infinitely. A few years ago, as critical dimensions approached 100 nm, a number of formidable challenges arose (1). It seemed that progress would slow, but during the past few years, device scaling has accelerated, as evidenced by several talks at the recent International Electron Devices Meeting [HN5] (IEDM) (2).

Today's electronic devices are based on the metal oxide semiconductor field-effect transistor (MOSFET) [HN6], which consists of source and drain electrodes, through which current can flow, and a gate electrode, which controls the current through the other two (see the figure). MOSFETs operate on a simple principle: When the gate voltage is low, an energy barrier prevents electrons from flowing from source to drain, whereas a high gate voltage lowers the energy barrier, allowing current to flow (see the figure). The gate electrode is separated from the silicon channel by a thin insulating layer to prevent the flow of gate current.

The MOSFET principle.

(Top) Minimum electron energy (Emin) versus position from source to drain (x) under high drain voltage. An increasing gate voltage lowers the energy barrier between source and drain. (Middle) Planar MOSFET with source (S), drain (D), gate, and doped silicon substrate. (Bottom) Double-gate MOSFET, with a gate above and below the undoped silicon film; channel length (L).

To comply with Moore's law, the transistor designer must shrink the distance between source and drain by a factor of ✓2 in each technology generation. This reduces the area by a factor of 2, thereby doubling the number of transistors per chip. Remarkable advances in subwavelength lithography [HN7] allow current-generation technologies with gate lengths of 65 nm to be manufactured. Economic considerations have not yet slowed progress, and state-of-the-art technology still operates far below fundamental limits imposed by thermodynamics and quantum mechanics (3). The serious transistor design issues arise from materials limitations and transistor physics.

For digital applications, a transistor switch must, first, deliver a large on-current that rapidly charges and discharges the capacitance of the wires connecting it to other transistors in the circuit. The switching power is proportional to the operating frequency and to the square of the power supply voltage. Transistor scaling increases the number of gates on a chip and their operating frequency. To limit power dissipation and prevent the chip from overheating, the power supply voltage must therefore decrease in each technology generation, while maintaining the on-current.

Second, a transistor switch should conduct very little current when off. However, as the distance between the source and drain shrinks, it becomes increasingly difficult to turn a MOSFET off. Because off-currents increase exponentially with device scaling, the off-state power consumption is now substantial.

Third, transistors should switch on abruptly as the gate voltage increases. However, because the current is controlled by thermal emission over an energy barrier, it takes a change in gate voltage of at least 60 mV to change the current by a factor of 10 at room temperature. As power supply voltages decrease, the voltage range between on and off states also decreases, and the 60-mV limit makes it difficult to obtain both high on-currents and low off-currents.

The challenge, then, is to engineer an appropriate energy barrier between source and drain so that the device can be turned off, while at the same time designing a gate structure that can effectively modulate the barrier and turn the transistor on. As channel lengths decrease, drain-induced electrostatic effects lower the barrier, thereby increasing the off-current and reducing gate control.

Drain-induced barrier lowering can be controlled by increasing the density of dopants in the silicon channel between source and drain. However, the thickness of the SiO2 gate insulator must be reduced to maintain gate control of the barrier. High channel doping and thin gate oxides lead to quantum mechanical tunneling [HN8], which increases leakage currents. Furthermore, the number of dopant atoms in the channel decreases with each technology generation, so that statistical fluctuations in their precise number lead to variations in device characteristics.

Several new transistor structures aim to improve the electrostatic control by the gate and mitigate the deleterious effects of dopants in the channel. For example, sophisticated two-dimensional channel doping profiles have been used to push the traditional, bulk-silicon MOSFET to channel lengths below 15 nm (4).

Other structures promise even better device scaling. In the silicon-on-insulator [HN9] MOSFET, the off-state barrier height is set by the gate-to-semiconductor work function difference rather than by channel doping. With extremely thin silicon films, channel lengths of 6 nm have been achieved (5). Gate control of the barrier is improved by placing a gate above and below the channel (see the figure). Several variations of this theme exist (6). In the FinFET [HN10], the silicon channel is a vertical “fin,” and the gates are placed on both sides of the fin (7). A FinFET with a 10-nm channel length has been reported (8). The gate-all-around MOSFET promises even better gate control (9).

Another route to smaller, faster transistors is the use of new materials. Silicon has been the material of choice for electronic devices because of its high-quality native oxide, but SiO2 films have been scaled to near their limit. Materials with higher dielectric constants would permit the use of thicker layers, which would decrease leakage currents (10). The use of channel materials with higher mobility could provide high on-currents at the low voltages needed to manage power.

Strained materials [HN11] have been shown to improve carrier transport substantially (11, 12), and manufacturing processes to introduce stress are being readied for production (13, 14). Germanium [HN12], the semiconductor originally used for transistors, is being reexamined because of the high mobilities that it provides (15, 16). For ultrahigh-speed applications (albeit with lower transistor counts than for silicon logic chips), high electron mobility transistors [HN13] (HEMTs) that use compound semiconductors rather than silicon have achieved speeds of 100 gigabits per second (17).

Recent developments in molecular electronics [HN14] are also promising. Carbon nanotube FETs [HN15] (18, 19) are particularly interesting because they might provide much better on/off-current ratios and device speed (20). Furthermore, because they are similar to MOSFETs, the sophisticated electronic design tools now in use might be extendable to carbon nanotube FETs. Alternatively, small molecules might be gated to realize single-molecule transistors (21). However, it seems unlikely that electrostatically gated molecular transistors could operate at channel lengths much smaller than those of silicon transistors (22).

Instead of using molecules to make transistors smaller, it may be preferable to complement silicon transistors with new types of molecular devices for applications such as high-density memory (23). But doing so will not be easy. Small devices tend to be dominated by effects at the contacts and can have high defect densities. They are likely to show wide variations in performance and often deliver low on-currents. Small electronic devices can operate at high frequencies, but high-speed operation of high-density circuits leads to unacceptably high power dissipation. Success will require both small devices and new information-processing schemes—perhaps inspired by biology—to make use of them.

Until now, chip performance has been driven by transistor scaling, but with the acceleration of Moore's law, transistors will reach their limiting size within a decade or so. A recent study concludes, however, that another 30 years of progress in silicon nanoelectronics is still possible (3). One approach, exploiting the third dimension by producing layers of devices on a chip, has recently been demonstrated (24). But as the number of devices per chip increases, the power dissipation per chip becomes a critical issue (3, 6). In the absence of expensive cooling systems, the power per chip is limited to about 200 W. Without innovative solutions, power dissipation constraints, not device physics or economics, will limit the number of transistors per chip.

Moore's law is about lowering cost per function, and molecular electronics might continue the trend without transistors by self-assembling new types of electronics on a Complementary MOS (CMOS) platform [HN16]. The future of electronics may lie in such heterogeneous systems that complement digital CMOS with new devices and information-processing schemes. For the past 30 years, we have known what to do: make transistors smaller. Progress continues at a breathtaking pace, but transistor scaling is approaching its limit. When that limit is reached, things must change, but that does not mean that Moore's law has to end.

HyperNotes Related Resources on the World Wide Web

General Hypernotes

Dictionaries and Glossaries

The xrefer Web site makes available a searchable collection of scientific dictionaries and other reference works.

A lexicon of semiconductor terms is provided by Intersil.

A dictionary of terms used in the semiconductor manufacturing industry is provided by Sematech.

A semiconductor glossary is provided by J. Ruzyllo, Department of Electrical Engineering, Pennsylvania State University.

The eEncylopedia is a dictionary of electronics-related terms offered by EE Times.

Web Collections, References, and Resource Lists

The Google Web Directory provides links to Internet resources in condensed matter physics and semiconductors.

Yahoo provides links to semiconductor Internet resources and semiconductor news. A collection of links to nanotechnology resources is also available.

BOIN's Semiconductor Linkpage includes pointers to companies, academic institutes, journals, organizations, and news sources in the semiconductor world.

The Semiconductor Subway, provided by the MIT Microsystems Technology Laboratory, provides links to semiconductor-related resources.

NanoLink provides links to nanotechnology sites on the Web.

The Nanotechnology Database provides sources of information on nanotechnology.

Online Texts and Lecture Notes

HyperPhysics is a tutorial on physics concepts presented by C. R. Nave, Department of Physics and Astronomy, Georgia State University. A section on semiconductor concepts is included.

Transistorized! is presented by PBS Online.

A semiconductor tutorial is available as part of the Materials Science and Technology Modules provided by the Department of Materials Science and Engineering, University of Illinois. A historical timeline is included.

The Lehrstuhl für Elektronische Bauelemente, University of Erlangen, Germany, offers an introduction to semiconductor technology.

Principles of Semiconductor Devices is a Web textbook provided by B. Van Zeghbroeck, Electrical and Computer Engineering Department, University of Colorado. A glossary is included.

Introduction to Microelectronics Manufacturing and Markets is hypermedia course by P. Schank and L. Rowe, made available by the Department of Electrical Engineering and Computer Sciences, University of California, Berkeley.

An online study guide for a course on electronic devices is provided by G. Lush, Department of Electrical and Computer Engineering, University of Texas, El Paso. A section on semiconductor fundamentals is included.

R. V. Jones, Division of Engineering and Applied Sciences, Harvard University, provides lecture notes, supplemental presentations, and other resources for a course on electronic devices and circuits.

J. Rabaey and A. Vladimirescu, Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, provide lecture slides in PDF format for a course on digital integrated circuits.

D. Gingrich, Department of Physics, University of Alberta, provides lecture notes for a course on instrumentation and electronics.

M. Shur, Electrical, Computer, and Systems Engineering Department, Rensselaer Polytechnic Institute, offers lecture slides for a course on advanced concepts in electronic and optoelectronic devices.

P. Ajayan and R. Siegel, Materials Science and Engineering Department, Rensselaer Polytechnic Institute, offer presentations for a graduate course on nanostructured materials.

General Reports and Articles

The 14 September 2001 issue of Science had a Viewpoint article by J. Meindl, Q. Chen, and J. Davis titled “Limits on silicon nanoelectronics for terascale integration.”

Scientific American makes available a collection of nanotechnology articles.

The Intel Technology Journal had an article (in the 4th quarter 1998 issue) by E. Meieran titled “21st century semiconductor manufacturing capabilities” and an article (in the 3rd quarter 1998 issue) by S. Thompson, P. Packan, and M. Bohr titled “MOS scaling: Transistor challenges for the 21st century.”

The vol. 46, no. 2-3, 2002 issue of the IBM Journal of Research and Development (a special issue "Scaling CMOS to the limit") had an article by H.-S. P. Wong titled “Beyond the conventional transistor.”

The 2002 update to the International Technology Roadmap for Semiconductors is available in PDF format (version 5 required).

The 1 January 2001 issue of Semiconductor International had an article by L. Peters titled “Ramping the 0.13 _m generation.”

Forbes makes available a 10 September 2002 article by A. Hesseldahl titled “Silicon shrinkage.”

Numbered Hypernotes

1. Logic chip and memory chip are defined by EE Times' eEncyclopedia.

2. Moore's law. The Webopedia has an entry for Moore's Law. Intel makes available a brief biography of Gordon Moore and a presentation titled “Expanding Moore's law.” Intel's Silicon Showcase provides a presentation on Moore's law and makes available (in PDF format) Moore's original 19 April 1965 Electronics paper titled “Cramming more components onto integrated circuits.” EE Times makes available a 11 November 2002 article by S. Ohr titled “Fate of Moore's law tops ISSCC agenda.” M. Frank, College of Engineering, University of Florida, offers lecture notes on Moore's law for a course on the physical limits of computing.

3. Semiconductors and the semiconductor industry. How Semiconductors Work on Marshall Brain's How Stuff Works Website offers an introduction to the principles of semiconductor materials. Sematech offers a presentation on how a chip is made. The IBM Microelectronics Web site offers an introduction to making semiconductors. A presentation on basic semiconductor theory is provided by International Rectifier. Britney's Guide to Semiconductor Physics is provided by C. Hepburn, a post-graduate student at the Department of Electronic Systems Engineering, University of Essex, UK. D. Palmer's Semiconductors-Information Web site provides introductions to semiconductors and links to semiconductor Internet resources. Semiconductor news and resources are provided by EE Times. The Semiconductor Industry Association offers a collection of industry Internet links and provides (in PDF format) a summary of the International Technology Roadmap for Semiconductors.

4. Transistors. Transistor is defined in xrefer's Dictionary of Science. The online Columbia Encyclopedia provides an introduction to the transistor. Bell Labs offers a presentation on the transistor; a technical backgrounder titled “What is a transistor?” is provided in PDF format. The Light Guide from the Australian Photonics Co-operative Research Centre includes a presentation on the transistor and its history. The Intel Education Web site offers presentations on how transistors work and how chips are made. The 1956 Nobel Prize in Physics was awarded to William Bradford Shockley, John Bardeen, and Walter Houser Brattain “for their researches on semiconductors and their discovery of the transistor effect.” IBM Research issued a 9 December 2002 press release titled “IBM announces world's smallest working silicon transistor.”

5. The International Electron Devices Meeting. The 2002 International Electron Devices Meeting (IEDM) Web site offers program information and abstracts. The illustrations from the IEDM keynote address by A. Grove titled “Changing vectors of Moore's law” are made available in PDF format by Intel. EE Times provides a 10 September 2002 article titled “IEDM sees strained, fully depleted future,” an 11 December 2002 article titled “IEDM: Intel, IBM joust at 90-nm,” and a 27 December 2002 article about the meeting titled “Scaling the mountaintop” (all by D. Lammers). AMD (Advanced Micro Devices, Inc.) issued a 9 December 2002 press release about breakthroughs presented at IEDM 2002.

6. Metal oxide semiconductor field-effect transistor (MOSFET). Field-effect transistor (FET) is defined in xrefer's New Penguin Dictionary of Science. FET and MOSFET are defined in Intersil's semiconductor lexicon. PBS Online's Transistorized! provides an introduction to FET and MOSFET. M. Shur makes available a slide presentation on field-effect transistors. D. Gingrich offers lecture notes on MOSFET for a course on instrumentation and electronics. G.-Y. Wei, Division of Engineering and Applied Sciences, Harvard University, provides lecture notes (in PDF format) on MOSFET devices for a course on electronic devices and circuits.

7. Advances in lithography. Lithography is defined in Intersil's semiconductor lexicon. IBM Research offers an introduction to optical lithography. P. K. Chu, Department of Physics and Materials Science, City University of Hong Kong, provides lecture notes (in PDF format) on lithography for a course on microelectronic materials and processing. The IBM Almaden Research Center offers a presentation on nanoscale lithography research. Intel's Silicon Showcase offers a presentation on advances in lithography. Numerical Technologies, Inc. offers a presentation on the subwavelength challenge. The September 2001 issue of Semiconductor Magazine had an article by K. Derbyshire titled “Next-generation lithography: Beyond 100 nm.” The 1 June 2002 issue of Semiconductor International had an article by A. Hand titled “NGL: Forever next-generation?” The May 2002 issue (on semiconductor technology) of the Intel Technology Journal had an article by P. Silverman titled “The Intel lithography roadmap.” Intel offers a presentation on extreme ultraviolet lithography.

8. Quantum mechanical tunneling is defined in E. Weisstein's World of Physics. A section on quantum tunneling is included in Todd Stedl's introduction to quantum mechanics. An introduction to quantum tunneling is provided in the glossary of physics and astronomy maintained by J. Schombert, Department of Physics, University of Oregon. Visual Quantum Mechanics offers an applet on quantum tunneling.

9. Silicon-on-insulator (SOI). SOI is defined in Intersil's semiconductor lexicon and in EE Times' eEncyclopedia. IBM Microelectronics offers an introduction to silicon-on-insulator (SOI) technology; a white paper on SOI technology is made available in PDF format. On 23 September 2002 EE Times published a collection of articles on SOI technology.

10. FinFET is defined in J. Ruzyllo's semiconductor glossary. C. C. Hu, Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, offers presentations on FinFET. AMD issued a 10 September 2002 press release about FinFET research titled “AMD announces technology to enable ten-fold performance leap in future transistors.”

11. Strained silicon technology. Strained silicon is defined in L. Ruzyllo's semiconductor glossary. EE Times had a 11 June 2002 article by D. Lammers titled “Technologist sketches IBM's silicon road map” that discussed strained silicon technology. IBM offers a press release and a presentation about strained silicon. ZDNet provides a 5 December 2002 article by J. Spooner titled “'Strained silicon' to pump up chips.” The 4 December 2002 issue of Semiconductor Business News had an article by M. LaPedus titled “IBM discloses combo strained-silicon/SOI technology.” The 1 November 2002 issue of Semiconductor International had an article by P. Singer titled “Strained silicon ready for prime time.” The September 2002 issue of Compound Semiconductor had an article by M. Bulsara titled “Strained silicon joins the drive to keep CMOS chips on course.” A strained silicon technology demo movie is provided by AmberWave Systems.

12. Information about germanium is provided by the WebElements Periodic table. PBS Online's Transistorized! includes a presentation on germanium use in early transistors. The new semiconductor materials Web site provided by the Ioffe Institute, St. Petersburg, Russia, includes a section on germanium.

13. High electron mobility transistor (HEMT). High electron mobility transistor (HEMT) is defined in a 4 December 2002 press release issued by Nippon Telegraph and Telephone Corporation. The Semiconductor Physics Group at COBRA (Inter-University Research Institute on Communication Technology), Eindhoven, Netherlands, offers a brief introduction to HEMT. M. Shur offers a slide presentation on HEMTs.

14. Molecular electronics. The February 2002 issue of Materials Today had a review article by M. Ratner titled “Introducing molecular electronics” and an insight article by K. Kwok and J. Ellenbogen titled “Moletronics: Future electronics.” EE Times had a 19 February 2002 article by C. Brown titled “Researchers close to delivering molecular circuits.” The 3 August 2001 issue of Science had a News Focus article on molecular electronics by R. Service titled “Assembling nanocircuits from the bottom up.” The 9 November 2001 issue of Science had an Enhanced Perspective about molecular-scale electronics by G. Tseng and J. Ellenbogen titled “Towards nanocomputers.” HP (Hewlett-Packard) issued a 9 September 2002 press release titled “HP announces breakthroughs in molecular electronics.” HP's Quantum Science Research Web site provides information about molecular electronics research at HP.

15. Carbon nanotube FETs. V. Crespi, Department of Physics, Pennsylvania State University, offers a presentation on carbon nanotubes. IBM makes available an introduction to carbon nanotubes and a 27 April 2001 press release titled “Chip evolution: IBM scientists develop breakthrough transistor technology with carbon nanotubes.” The Nanoscale Science Department at IBM Research offers a presentation on carbon nanotubes with a section on the nanotube field-effect transistor and a collection of publications on carbon nanotubes and nanotube electronics. IBM Research offers a presentation titled “Building carbon nanotube transistors.” Nature makes available a 9 August 2001 Feature of the Week on carbon nanotubes. The 2 August 2002 issue of Science had a review article by R. Baughman, A. Zakhidov, and W. de Heer titled “Carbon nanotubes — The route toward applications.”

16. CMOS is defined in J. Ruzyllo's semiconductor glossary and in Intersil's semiconductor lexicon. The June 2002 issue of Materials Today had an article (available in PDF format) by G. Marsh titled “IMEC pushes the limits of CMOS.”

17. M. Lundstrom is in the School of Electrical and Computer Engineering, Purdue University.

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