Review

Silicon Device Scaling to the Sub-10-nm Regime

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Science  17 Dec 2004:
Vol. 306, Issue 5704, pp. 2057-2060
DOI: 10.1126/science.1100731

Abstract

In the next decade, advances in complementary metal-oxide semiconductor fabrication will lead to devices with gate lengths (the region in the device that switches the current flow on and off) below 10 nanometers (nm), as compared with current gate lengths in chips that are now about 50 nm. However, conventional scaling will no longer be sufficient to continue device performance by creating smaller transistors. Alternatives that are being pursued include new device geometries such as ultrathin channel structures to control capacitive losses and multiple gates to better control leakage pathways. Improvement in device speed by enhancing the mobility of charge carriers may be obtained with strain engineering and the use of different crystal orientations. Here, we discuss challenges and possible solutions for continued silicon device performance trends down to the sub-10-nm gate regimes.

The steady reduction in the minimum feature size in integrated circuits has helped the microelectronic industry to produce products with spectacular increase in computational capability and integration density at lower cost. Smaller transistors operate faster than larger ones, and for a given chip technology, the cost of a chip decreases with area rather than with the number of transistors.

The exponential scaling trend surely will eventually hit fundamental limits, but the many predictions of a near-term end of device scaling have proven too pessimistic. With the introduction of the production of 90-nm node technology in 2004, the semiconductor industry is entering the “nano” era (1). (The “90-nm node” refers to the smallest half-pitch metal lines available in the technology. The actual gate lengths of the devices are about 50 nm.) In the next decade, device gate lengths will be scaled to below 10 nm (1). We discuss below the challenges in device scaling and possible solutions in maintaining the performance trend.

MOSFETs: The Building Blocks

The MOSFET, or metal oxide semiconductor field-effect transistor, is a fundamental switching device in very-large-scale integrated (VLSI) circuits. A MOSFET (Fig. 1A) has at least three terminals, which are designated as gate, source, and drain. The gate electrode is separated electrically from the source and the drain by a thin dielectric film, usually silicon dioxide. The source and the drain are doped with impurities that are opposite in polarity to the substrate, which is doped with boron for N-channel transistors and with arsenic or phosphorous for P-channel transistors. This source, substrate, and drain doping effectively produces two back-to-back junction diodes from the source terminal to the drain terminal. When a sufficiently large positive voltage is applied to the gate of an N-channel transistor (which creates an electric field, hence the field effect), the silicon surface is “inverted”—the conduction band is populated and forms a narrow conducting layer between the source and the drain. If there is a voltage difference between the source and the drain, an electric current can flow between them. When the gate voltage is removed or set at zero voltage, the surface region under the gate is depleted with electric carriers and there is no current flow between the source and the drain. We can therefore see that the current flowing through the structure can be regulated by applying voltage to the gate electrode.

Fig. 1.

(A) Schematic of MOSFET indicating various relevant device scaling parameters. (B) Complementary metal-oxide semiconductor (CMOS) inverter gate delay as a function of power-supply voltage (Vdd). Gate delay rapidly increases as Vdd approaches the threshold voltage (Vt). (C) Design space for supply and threshold voltages for optimum performance and power dissipation. Technology scaling diminishes this design space.

A MOSFET can be used either as an electrical switch or as an amplifier. The majority of MOSFETs on an integrated circuit today are used as electrical switches. How fast a MOSFET can be switched on and off is therefore a critical figure of merit to determine the competitiveness of the technology. The two major factors that control the speed of MOSFETs are the channel length from the source to the drain and the speed at which channel charge carriers travel from the source to the drain. We will discuss these two factors in more detail below.

Shrinking the Transistor

Shrinking transistors not only packs more devices into a given area but also shortens the distance between source and drain, or the gate length, which can improve the switching speed. The two challenges in decreasing MOSFET size are fabrication and maintaining performance. The backbone of MOSFET fabrication is a process called lithography, which resembles the printing of a photograph by shining light through a negative onto a photosensitive surface. Lithography allows complex patterns to be created through a series of printing and etching steps. The ability to print ever-smaller fine lines is mandatory for continued device scaling. Advanced photo-lithography techniques have enabled the industry to keep pace with the demand imposed by increasingly smaller structures. However, the smallest feature size is related to the fundamental limit of wavelength used in conventional optical lithography. Alternative technologies capable of writing features far smaller than those produced by conventional optics have also been demonstrated and include the use of extreme ultraviolet (EUV) radiation, x-rays, and electron beams. Recently, the self-assembly process has attracted much attention because of its potential in producing nano-scale patterns. The concern is whether any of these alternatives can be scaled up to meet the throughput, control, and cost requirements for manufacturing.

Given the ability to create smaller device features, to what extent can the gate length be reduced before the MOSFET ceases to function as a switch? The gate terminal can lose the control of channel electric carriers when the source and the drain are brought into proximity without scaling other device parameters. Eventually, the gate terminal cannot turn off the devices, and transistor action can no longer be observed. This phenomenon is the so-called short-channel effect (SCE). According to the scaling theory of Dennard (2), the vertical dimensions (gate-oxide thickness, junction depth, and depletion width) must be scaled down with the lateral dimensions such as gate length. This theory guarantees appropriate electrostatic characteristics when a larger device is scaled down to a smaller one (Fig. 1A). The industry has been by and large following this scaling guideline for shrinking MOSFETs to gain higher density and speed without degrading reliability and power.

The accelerated gate-length scaling in the past decade has pushed many vertical device parameters to their fundamental or technological limits. For example, gate oxide now consists of only a few atomic layers; alternative gate materials with a higher dielectric constant are needed. It is also difficult to produce an extremely shallow and abrupt junction without increasing the external resistance. (Junction resistance is inversely proportional to junction depth.)

Ion implantation has been the dominant process for the creation of shallow junctions. A high-temperature annealing process is needed to repair the damage to the single crystal and to activate the dopant atoms. During this step, diffusion and redistribution of dopant atoms occur. A high-temperature, short time scale annealing process is more desirable to produce shallow and abrupt junctions. A near-zero thermal-budget junction technology, such as millisecond flash-lamp and laser annealing, will be required.

Finally, the increase in channel doping needed for SCE control will substantially increase the junction capacitance and leakage. All of these changes degrade device performance. The problem is exacerbated by the “nonscaling” factors that arise when the traditional MOSFET design is scaled.

Nonscaling Factors

As pointed out above, several factors do not scale as we shrink MOSFETs. The subthreshold nonscaling issue is the most fundamental one (3). A MOSFET is turned on when a sufficiently high voltage is applied to the gate. The voltage above which the MOSFET is turned on is loosely defined as threshold voltage. The leakage current in the off state depends exponentially on the threshold voltage. Ideally, one would keep the threshold voltage high to minimize the power consumed when the device is off (the stand-by power) and to ensure an appropriate noise margin. The supply voltage is usually reduced in device scaling to keep the active power manageable and to ensure reliability. However, higher device performance will require as much gate overdrive (the excess voltage applied above the threshold) as possible, because higher driving voltages lead to faster switching. Figure 1B shows the circuit delay as a function of supply voltage, Vdd. Performance can only be maintained by keeping threshold voltages low, but the threshold voltage cannot be scaled down much without causing a substantial increase in leakage current in the off state. The proper choice of Vdd and threshold voltage for best performance and power tradeoff depends on the application. The design window rapidly diminishes as technology is scaled down (Fig. 1C). In addition, the aggressive reduction in gate dielectric has also caused exponential increase in gate leakage.

Together, these effects have caused the so-called power crisis in the silicon chip industry. Power management has now become the number one issue in any high-performance and low-power application. Currently, there is a consensus that maintaining the device performance trend with conventional device scaling technique is extremely challenging, if possible at all. New device structures and materials will be needed to sustain the current rate of progress in device technology.

Possible Solutions for Device Scaling

Circuit performance can be improved by building conventional MOSFETs on a silicon-on-insulator (SOI) substrate (Fig. 2A). The insulator layer can be created by implanting oxygen ions and then annealing the layer to form an oxide. The addition of an oxide layer below the transistor junction SOI layer can effectively reduce the junction capacitance and leakage current. It also eliminates the so-called “reverse body effect” (4) in stacked circuits. As a result, SOI technology offers a faster circuit and consumes less power.

Fig. 2.

Device schematics and cross sections for (A) SOI MOSFET, (B) UTSOI MOSFET, and (C) FinFET double-gate MOSFET.

Ultrathin SOI (UTSOI) MOSFET is an attractive option for device scaling, because it can effectively reduce the SCE and eliminate most of the leakage paths (57). For thicker SOI channels, the drain field could easily penetrate to the source side through the channel or buried oxide when the gate length is reduced. However, a thin SOI channel can resolve this problem. Based on this concept, a functional transistor with a gate length of 6 nm was demonstrated (Fig. 2B) by using an ultrathin channel of 4 to 8 nm and aggressive “halo” (8) implantation (6). This extremely small silicon MOSFET was functional, but its device drive current suffered from channel mobility degradation and high external resistance.

The integration of ultrathin SOI channels into the conventional MOSFET process is quite challenging. The gate and spacer modules must be carefully designed to prevent substantial silicon consumption. The ion implantation process for the source/drain extension should be designed to minimize loss of dopant dose and to avoid complete amorphization of the silicon layer by the ion implantation process. A thin gate spacer coupled with the raised-source-drain process has been shown to be effective in minimizing external resistance without compromising parasitic capacitance. With this new process scheme, improved drive currents were realized (9).

Setting and controlling the threshold voltage in devices with such thin SOI layers is also quite challenging. Conventional doping schemes may not be effective as a result of doping fluctuation. One attractive process option is to completely “silicide” the polycrystalline-silicon gate stack by converting the polysilicon to a metal silicide. The gate work function can be adjusted over a substantial range by alloyed silicide and ion implantation to the gate before silicidation (7). Although the external resistance can be reduced by process improvement, the mobility degradation in thin SOI channels could be a fundamental issue. The channel mobility is substantially reduced at SOI thicknesses below 10 nm. This decrease may be caused by a “surface roughness”–like scattering mechanism that results from the perturbation of band potential by variations in the SOI layer thickness (10).

The ultrathin SOI thickness requirement for SCE control in single-gate FETs can be relaxed by using a more complex “double-gate” FET that offers improved electrostatic gate control of the body. There are many review articles on double-gate devices (1113). The symmetric nature in a double-gate FET reduces the depletion width by 50% compared with that of a single-gate structure. In addition, there is no drain-to-body fringing field through the buried oxide (BOX) (Fig. 2A) in a double-gate structure. Numerical simulations indicate that scalability for double-gate FETs improves by a factor of 2.5 to 3 (5). Because the double-gate device operates at much lower vertical electric fields, the mobility requirement in double-gate devices can be lower than that of conventional planar MOSFETs (14).

Double-gate FETs can be fabricated in planar (14, 15), vertical (16), and finlike (1719) structures. Of all the double-gate device structures, the FinFET is the simplest to implement. The body of a FinFET device consists of a vertical crystalline silicon wall (Fig. 2C). The gate wraps around both sides of the fin and creates a channel on each side of the fin. In a FinFET, the two channels are perpendicular to the wafer surface and the current direction is parallel to the wafer surface. High current has been demonstrated when the FinFET structure is combined with a raised-source-drain process.

Enhanced Mobility: Making Carriers Travel Faster

Mobility enhancement is an attractive option, because it can potentially improve device performance beyond any of the benefits from device scaling. The two main approaches being pursued are strain engineering (both process-induced and substrate-induced) and orientation effects (Fig. 3).

Fig. 3.

Device cross sections for (A) strained silicon on insulator (SGOI), (B) strained silicon directly on insulator (SSDOI), and (C) hybrid-orientation technology (HOT).

Strain engineering. Strain effects induced during the fabrication process can increase the channel mobility. Both tensile and compressive stresses can be introduced in any one of the three dimensions by process techniques (2027). The electron and hole mobility respond differently to uniaxial stresses (Fig. 4).

Fig. 4.

Possible directions of uniaxial stresses and their effects on N-channel and P-channel MOSFETs.

The most effective way to introduce high tensile strain to the channel is to epitaxially grow strained silicon on a relaxed silicon germanium (SiGe) layer. Because of the lattice mismatch between silicon and SiGe, the lattice of the silicon layer is stretched (strained) in the plane of the interface. This deformation breaks the symmetry of the energy-band structure and results in band splitting (Fig. 5). The reduced interband/intervalley scattering and effective masses result in enhanced carrier transport in the strained-silicon layer that is used as the channel of the MOSFET. Enhanced drive currents of 15 to 25% have been demonstrated on sub-100-nm bulk strained-silicon MOSFETs (20). The performance benefit of combining strained silicon with an SOI substrate has also been demonstrated in a 60-nm gate length, N-channel MOSFET with ultrathin thermally mixed strained silicon/SiGe on insulator substrate (28). The presence of the SiGe layer in strained-silicon substrate leads to several challenges related to materials and integration, such as a high density of defects in strained silicon on relaxed SiGe induced by the strain relaxation in SiGe and a substantial difference in doping diffusion property in SiGe. (Boron diffusion is retarded, whereas arsenic diffusion is enhanced as compared with the diffusion in silicon.) Such challenges require additional efforts in junction engineering to control SCEs and to set the MOSFET threshold voltages to the desired values. Substantial device self-heating is also observed in strained silicon/SiGe devices because of the lower thermal conductivity in SiGe. Recently, Rim et al. (29) demonstrated transistors using ultrathin strained silicon directly on insulator (SSDOI) structures that eliminate the SiGe layer before transistor fabrication, thereby providing higher mobility while mitigating the SiGe-induced material and process integration problems.

Fig. 5.

Biaxial stress effects on the conduction and valence bands of strained silicon.

An SSDOI structure is fabricated by a layer-transfer or “wafer-bonding” technique. First, an ultrathin layer of strained silicon is formed epitaxially on a relaxed SiGe layer, and an oxide layer is formed on top. After hydrogen is implanted into the SiGe layer, the wafer is flipped and bonded to a handle substrate. A high-temperature process splits away most of the original wafer and leaves the strained-silicon and SiGe layers on top of the oxide layer. The SiGe is then selectively removed and transistors are fabricated on the remaining ultrathin strained-silicon. A fabricated SSDOI device structure is shown in Fig. 3A. Both electron and hole mobility enhancement have been observed, which indicates that strain is retained after the device-processing steps have been completed (29).

Crystal orientation effects. The carrier mobility of inversion layers depends on surface orientations and current flow directions. For P-channel MOSFETs, hole mobility is 2.5 times as high on (110) surface orientation as on a standard wafer with (100) surface orientation (30). However, electron mobility is highest on (100) substrates. To fully realize the advantage of the carrier mobility dependence on surface orientation, a new technology has been developed to fabricate complementary metal-oxide semiconductor (CMOS) on hybrid substrates with different crystal orientations, with NFETs on silicon of (100) surface orientation and PFETs on (110) surface orientation (31). In this hybrid-orientation technology (HOT), layer-transfer process, block-level trench etch, and epitaxial regrowth were performed before the conventional CMOS device process. A cross section of CMOS on hybrid substrate is shown in Fig. 3C, with NFET on (100) SOI and PFET on (110) silicon epitaxial layer. The hybrid substrate was formed by layer-transfer technique through wafer bonding. First, hydrogen was implanted into an oxidized silicon substrate. The wafer was then flip-bonded to a handle wafer with different surface orientation. A two-phase heat treatment was then carried out to split the hydrogen-implanted wafer and strengthen the bonding. Finally, the top SOI layer was polished and thinned down to the desired thickness. A substantial PFET performance enhancement was demonstrated on 90-nm-node CMOS devices.

Threshold voltage roll-off behavior, junction leakage current, overlap, and junction capacitances are all very similar between (110) and (100) substrates, which indicates similar dopant diffusion characteristics for these orientations. The HOT technology is clearly an attractive option to improve device performance without introducing new material. However, the impact on circuit performance of mixing SOI and bulk devices on the same chip will require more detailed analysis.

Viability: The Crucial Issues

The 2003 version of the International Road-map for Semiconductors (1) projected that, by 2016, sub-10-nm gate-length MOSFETs will be in production with equivalent oxide thicknesses of 5 Å and junction depths below 10 nm. Although functional MOSFETs with sub-10-nm gate lengths have been demonstrated using UTSOI substrate, manufacturability problems of sub-10-nm gate devices remain to be resolved. First, gate stacks with higher dielectric constants and metal gate electrodes are needed to mitigate the gate leakage problem. Second, alternative doping techniques are required to produce shallow and abrupt junction profiles without severely increasing the external resistance. Third, alternative device structures such as UTSOI and double-gate structures will likely be needed for sub-10-nm gate devices.

Additional sources of performance gain are also needed to compensate for any degradation from the subthreshold nonscaling phenomenon. Mobility-enhancement technique is attractive, because it provides performance enhancement in addition to any benefits derived from device scaling alone. Straining the silicon crystal and building N-type and P-type MOSFETs on different crystal orientations are promising methods for mobility enhancement. In fact, some form of strained-silicon techniques are already being used in silicon integrated-circuit manufacturing. Some scaling and mobility-enhancement options can be combined for even higher performance gains. One example that integrates both UTSOI and FinFET devices on the same wafer and that enables hybrid orientation was reported by Doris et al. (32).

The growing power density and the diminishing process margin of sub-10-nm gate-length MOSFETs cannot be dealt with by process technology alone. Overall system performance gain will require optimization among the technology, circuit, packaging, and architecture levels.

References and Notes

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