PerspectiveApplied Physics

Toward a Universal Memory

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Science  22 Apr 2005:
Vol. 308, Issue 5721, pp. 508-510
DOI: 10.1126/science.1110549

When it comes to computers, mp3 players, digital cameras, and other electronic gadgets, there is no such thing as too much memory. Whether it is more Flash memory for taking high-resolution digital pictures, a bigger hard drive for digital video files, or more random access memory (RAM) to view them on the computer, the appetite for ever more memory at ever-increasing densities appears insatiable. An emerging technology, magnetoresistive RAM, promises additional functionality and improved memory performance that will enable yet more applications and open up system designs that are not possible today.

Today's dominant solid-state memory technologies—static RAM, dynamic RAM, and Flash—have been around for a long time, with Flash the youngest at 21 years (1). Their longevity can be explained in part by mutually beneficial differentiation. Each technology does a single thing very well, but many systems need all three memory types to deliver overall good performance at reasonable cost. However, the gain from differentiation comes at the cost of increased system and fabrication complexity, particularly in so-called embedded applications, where an entire electronic system is implemented on a single chip with static RAM, dynamic RAM, and Flash often used side-by-side.

All three technologies have advantages and disadvantages. Static RAM has excellent read and write speeds, integrates readily into the process technology of embedded applications, and requires little power for data retention. However, its large cell size (a typical memory bit requires six transistors) makes it impractical for embedded applications that require a lot of memory. Embedded static RAM is used for cache memory in microprocessors, where high speed is more important than large amounts of memory.

Dynamic RAM uses a single transistor and a storage capacitor per cell and thus provides a denser architecture than static RAM, at the expense of increased embedded-process complexity. Because the stored charge tends to leak out of the capacitor, dynamic RAM requires constant power to refresh its bit state every few milliseconds. Because of its high power consumption, large amounts of dynamic RAM are impractical for portable electronics with limited battery life.

In contrast to static and dynamic RAM, Flash memory offers nonvolatile data storage; that is, its information is not lost when the power is turned off. Nonvolatility is highly desirable in portable electronics, because nonvolatile data retention does not consume any battery power. Flash also has high density and moderately fast read access time, but its write mode is too slow and its write endurance far too limited for many applications. In addition, embedded Flash needs its own high-voltage drivers, complicating the design and manufacturing process.

For some time, researchers have tried to devise nonvolatile alternatives to Flash. The goal is a “universal memory” that combines the best attributes of static RAM, dynamic RAM, and Flash. Such a memory would eliminate the need for multiple memories in many applications, would improve system performance and reliability by avoiding data transfer between multiple memories, and would reduce overall system cost.

Magnetoresistive RAM (MRAM) is currently the most promising contender for a memory with such universal characteristics. It combines nonvolatility with relatively high read and write speeds and unlimited endurance. Furthermore, the MRAM storage element resides in the metal interconnect layers, well above the silicon, allowing its process to be optimized independently from the underlying semiconductor process. MRAM is therefore cost effective to integrate and is ideally suited for embedded-memory applications.

2D write selection with MRAM. (Left)

MRAM bit cell with a magnetic tunnel junction in series with a transistor for bit read selection. Perpendicular write lines above and below the magnetic tunnel junction select a single tunnel junction during programming. (Right) Top view of an MRAM array, highlighting the fully selected bit (red) in the center and 1/2-selected bits (blue) along each current-carrying write line. In toggle-MRAM, all bits are oriented at 45° with respect to the write lines.

State-of-the-art MRAM combines a magnetoresistive magnetic tunnel junction with a single-pass transistor for bit selection during read (see the figure) (2). The tunnel junction has a free magnetic layer, a tunneling barrier, and a fixed magnetic layer. The magnetization of the fixed layer is prevented from rotating, whereas the magnetization orientation of the free layer can be switched and is used for information storage. The resistance of the tunnel junction depends on the relative magnetization orientation of the free layer with respect to the fixed layer. For tunnel junctions with a NiFe free layer and an aluminum oxide tunneling barrier, the maximum difference in resistance (the magnetoresistance) is about 40 to 50%.

To read a single bit, the transistor is turned on, a bias of ∼0.3 V is applied to the bit, and the memory state is determined by measuring the amount of current that flows through the bit. Programming is achieved by passing current through two perpendicular write lines, one above and the other below the selected bit; these are respectively termed the “bit line” and the “digit line” (see the figure). The lines are clad with magnetic material to focus the applied field to the bit for improved write selectivity and increase the field magnitude by a factor of ∼2, reducing the write power consumption by a factor of ∼4.

MRAM faces several challenges before it can be introduced to the market on a large scale. The first challenge relates to the switching current distribution. The two-dimensional (2D) write selection scheme outlined above requires tight and uniform switching current distributions. Successful programming of the selected bit requires that the combined write field from both write lines must be greater than the bit's switching field. In addition to the selected bit, thousands of bits along the two write lines (called 1/2-selected bits) see 71% of the write field. As a consequence, a 4-Mb memory will suffer 1/2-select disturbs, unless the standard deviation of the bit-to-bit switching current due to inevitable material and processing variations is less than 6%. Because the 1/2-select disturb process is thermally activated, the actual distribution must be even tighter to ensure proper operation over the life of the memory (typically 10 years).

As a solution to the 1/2-select problem, the late Leonid Savtchenko of Motorola proposed a novel free-layer structure and a phase-sensitive write pulse scheme, in which the free layer rotates rather than switches (3). A full rotation takes place only if a bit sees both field pulses; as a result, 1/2-selected bits are less susceptible to thermal activation than are unselected bits. Because the free-layer rotation toggles the bit state, unipolar write currents can be used, further simplifying the design. A necessary pre-read before write effectively reduces the number of write pulses by 50%. This toggle-write method is used in the 4-Mb MRAM under development at Freescale Semiconductor (4).

A different approach is taken by Cypress Semiconductor, whose 256-kb lower density MRAM avoids the 1/2-select problem altogether by having individual write transistors for each bit. This design can also reduce the overall write current, but it comes at the cost of increased cell size.

The second concern for MRAM is its relatively small readout signal, which effectively limits its read speed. The available signal is roughly proportional to the magnetoresistance divided by the bit-to-bit resistance distribution. IBM has obtained read times of 3 ns (3 × 10−9 s) in 1-kb research memories, Freescale has demonstrated a 25-ns cycle time for its 4-Mb MRAM (5), and Cypress Semiconductor is targeting a 70-ns cycle time for its 256-kb MRAM (6). However, a magnetoresistance of more than 230% was recently demonstrated in junctions that use MgO as the tunneling barrier (7, 8). Use of this material could lead to much faster MRAM operation, provided the resistance distributions are as tight as for aluminum oxide barriers.

As with any new technology, customers will worry about its long-term reliability. The most obvious concerns relate to the long-term stability of the ultrathin tunneling barrier, the stability of the magnetic layers in the free layer, and data retention. Accelerated tests show that these mechanisms have negligible impact on memory performance at operating conditions.

The tunneling barrier is likely to be highly stable, because aluminum oxide has a high breakdown voltage even at very small thicknesses, MRAM uses a low operating voltage, and only the magnetic tunnel junctions that are being read are subject to any voltage stress. Accelerated dielectric breakdown studies indeed show barrier lifetimes far greater than 10 years (9). Interdiffusion between the magnetic layers may affect the switching performance over time, but accelerated tests indicate that over 10 years of use, virtually no change in switching performance at operating temperatures would occur. MRAM data retention is inversely proportional to the thermal flip rate of the free layer, but at present bit dimensions, accelerated tests predict no observable thermal flip rate at operating conditions.

Future generations of MRAM will use smaller tunnel junctions and will thus have to readdress the above challenges. Going toward smaller dimensions must not introduce more bit-to-bit variations or jeopardize data retention. The switching current will not substantially increase with reduced bit size (provided that other dimensions, such as the proximity to the write lines and their width, also decrease). But the current density will scale inversely with the conductor area, and electromigration may therefore become an issue. At that point, spin momentum transfer (10)—switching by a spin-polarized current through the bit—might become a viable alternative to 2D write selection.

This year, Cypress Semiconductor became the second company (after Freescale Semiconductor) to announce that it has shipped fully functional MRAM samples to potential customers. Many other companies have demonstrated multi-Mb MRAM prototypes. It is now only a matter of time before the first volume shipments of MRAM devices take place.

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