Review

Magnetic Domain-Wall Logic

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Science  09 Sep 2005:
Vol. 309, Issue 5741, pp. 1688-1692
DOI: 10.1126/science.1108813

Abstract

“Spintronics,” in which both the spin and charge of electrons are used for logic and memory operations, promises an alternate route to traditional semiconductor electronics. A complete logic architecture can be constructed, which uses planar magnetic wires that are less than a micrometer in width. Logical NOT, logical AND, signal fan-out, and signal cross-over elements each have a simple geometric design, and they can be integrated together into one circuit. An additional element for data input allows information to be written to domain-wall logic circuits.

Conventional microelectronic integrated circuits (ICs) work by controlling the flow of electrons through transistor switches. Digital signals are represented in the IC by the presence or absence of electrical charge (Table 1). Electrons can offer more, however. In addition to electrical charge, electrons also possess the quantum mechanical property of spin. Unlike electrical charge, however, spin can have two directions, conventionally known as “up” and “down,” permitting alternate representations of binary digits. For example, the magnetization of a small ferromagnetic element is the classical limit of electron spin and has long been used to store information in magnetic recording. During the last decade, a number of researchers have been building the new technology of spintronics, in which the spin and the charge of the electron are used in microelectronic ICs to represent bits and carry out data processing. In general, this technique promises lower-powered, higher-speed, nonvolatile devices with which to build the next generation of computing technology (1, 2).

Table 1.

Symbols for electronic logic, together with the appropriate CMOS circuit element and a schematic drawing of the optimized domain-wall logic element (dimensions shown refer to the design rule used here of 200-nm–wire width connecting logic elements and 1-μm turning radius of corners). The fan-out, cross-over, and logical AND junctions all contain tapered regions to connect to the 200-nm-wide wire links. Vdd is the supply voltage.

Spintronics development has followed different approaches in the semiconductor and magnetism communities. The semiconductor approach involves creating and manipulating spin-polarized electrons in a semiconductor host, with information being represented as either spin “up” or spin “down.” At the moment, the lack of a suitable room-temperature ferromagnetic semiconductor has limited the development of functioning devices (3), although much progress has been made in understanding the manipulation of spin in semiconductors by using optical probes (4).

The magnetism community has taken a different tack. After the discovery of giant magnetoresistance exhibited by metallic ferromagnetic/nonmagnetic multilayers (5), researchers have developed a large number of room-temperature devices by using ferromagnetic metals such as nickel, iron, and cobalt (1). Information is represented in these devices by the direction of magnetization in a small ferromagnetic element. One such device, called a magnetic tunnel junction (MTJ), forms the building block of magnetic random-access memory (MRAM), which is a nonvolatile, high-density, high-speed memory technology close to commercialization (6). Furthermore, recent demonstrations of the spin-momentum transfer effect (711), in which magnetization is operated on directly by an applied current, have added further heat to this already-exciting field by providing a new interface mechanism between the worlds of electronics and magnetism. We and other researchers have been working to extend magnetic nonvolatile memory to develop the required elements for viable magnetic logic technologies.

Magnetic logic. Digital microelectronics is a combination of memory and logic. The basic Boolean logic functions, such as AND, NOT, and XOR, allow the digital IC to combine numbers from memory in arithmetic calculations. MRAM is manufactured using a complementary metal-oxide semiconductor (CMOS)–compatible process and will, therefore, indirectly affect microelectronic logic by allowing large amounts of high-speed, high-density, nonvolatile memory to be embedded with the semiconductor microprocessor. The emerging field of magnetic logic seeks to redesign the principles of operation of microelectronic logic at the lowest level to make direct use of ferromagnetism.

Attempts have been made (1214) to implement magnetic logic based on a single-electron transistor architecture designed by the University of Notre Dame (15). These schemes, called magnetic cellular automata, use a network of magnetostatically coupled magnetic elements. Information propagates by magnetic solitons running across the lattice of interacting magnetic elements, and logic functions are performed by summing stray magnetic fields at nodal dots that have well-defined switching thresholds. One of the challenges with such schemes is that the magnetostatic interaction field between ferromagnetic elements is usually weaker than the demagnetizing field within the element; consequently, any physical defects in the shape of the magnetic elements tend to block the propagation of information, and the device becomes excessively intolerant to fabrication faults.

A number of MTJ-based magnetic logic schemes have been proposed. In one class of these (1618), information enters into the logic gate by the currents in multiple bit lines. The so-called “free layer” of the MTJ will rotate into the direction of the net magnetic field from the combined currents, effectively acting as a nonlinear summing element. This in turn changes the resistance of the junction, which can be used to control the current in subsequent bit lines. Such a scheme has a number of advantages, including that the devices are based on existing MTJ technology and that the logic function can be programmed by changing the magnetization direction of the reference layer in the MTJ. This makes MTJs attractive for field-programmable gate arrays (19), where many different applications use the same hardware; the precise hardware function is defined by programming a configuration of the storage elements. Perhaps even more appealing is the prospect of on-the-fly reconfigurability, because the function-defining magnetic hard layer can be reversed in nanoseconds, allowing hardware to adaptively track the optimized architecture for the computation in hand (1). A disadvantage of these schemes is that high current densities must be switched every time the data change, a process which requires high magnetoresistance ratios and large transistors. A variation on this theme exists, in which an MTJ is used to bias a conventional electronic logic gate (20). In this case, the MTJ is only used to define the logic function; the actual computation is performed entirely in classical electronics.

As an alternative, we have developed a magnetic logic architecture referred to as “domain-wall logic,” which uses no transistors and exhibits very little heating caused by data switching. A domain wall is a mobile interface between regions of oppositely aligned magnetization. In particular, a submicrometer planar nanowire made from a soft magnetic material such as Permalloy (Ni80Fe20) has been shown to form an excellent conduit for domain walls (2123). The high shape anisotropy of the nanowire ensures that magnetization prefers to align with the long axis of the wire. These two possible directions form the basis of the binary information representation (Table 1), with a magnetic domain wall acting as the transition edge in a changing signal. Domain walls can be propagated through complex networks of nanowires under the action of an externally applied magnetic field. This field rotates in the plane of the device and acts as both the clock and the power supply. Previous work (24) has shown how a cusp-shaped planar nanowire can be used to reverse the direction of magnetization. Given that we define a logical “1” as the magnetization pointing in the direction of propagation of domain walls and a logical “0” as the magnetization opposing the direction of propagation of domain walls, the cusp in effect performs the logical NOT operation. In order to implement any arbitrary logic function, it is necessary to have some additional basis functions. At least one two-input function, such as AND or OR, is required to complement the NOT function so that any computational calculation can be performed. Two routing functions are also required for most complex logic circuits: a fan-out structure, which makes two identical copies of an input signal; and a cross-over structure, which allows two signals to pass over each other without interference. It is also necessary that the applied magnetic field requirements of the functions should be mutually compatible, so that a single global rotating magnetic field can be applied to the entire circuit, with all of the different functions operating together. We have found that this can be achieved for an architecture consisting of logical NOT, logical AND, fan-out, and cross-over junctions (Table 1). Furthermore, we have developed a field-addressable data-input element for providing logic circuits with data on which to operate. We describe the development of these devices below.

Domain-wall logic elements.Figure 1A shows a magnetic logic circuit made up of a NOT-gate cusp, a fan-out junction, and a cross-over junction (25). For measurement, the entire circuit was placed in a rotating magnetic field. As shown previously (24, 26), the NOT gate was fabricated in a loop structure to ensure that at least one domain wall existed in the loop and to enable easy experimental testing. What is new here, however, is that a domain wall propagating around the loop in Fig. 1A must also pass through a cross-over structure, as indicated schematically in Fig. 1B. To obtain a well-defined starting state of a single domain wall before measurement, the device magnetization was first saturated in a large (>200 Oe) magnetic field before adjacent pairs of domain walls were annihilated by using a low-amplitude rotating field, as before (26). Because of the synchronous nature of the logic device, circuit geometry defined the domain-wall propagation time around the NOT gate/loop to be 0.5 field cycles through the NOT gate and 1 field cycle for each 360° loop. Hence, a single domain wall round trip should take 2.5 field cycles, leading to a 5–field cycle magnetization switching period. The fan-out element formed part of this loop but did not affect the domain wall round-trip time. One fan-out output fed back into the loop, whereas the other extended into a long arm to provide a monitor of the loop magnetization.

Fig. 1.

(A) Focused ion beam (FIB) image of a magnetic nanowire loop containing a NOT gate, fan-out junction, and cross-over junction. Only the bright lines indicate the presence of magnetic material; all other features are artifacts of the fabrication process. The directions of rotating field components (Hx and Hy), and the sense of field rotation (Rot) are indicated, and the asterisk denotes the position of MOKE measurement. (B) Schematic diagram with arrows illustrating the route of a domain wall propagating through the magnetic structure within a counterclockwise rotating field. (C) MOKE trace obtained from the position marked with an asterisk of the nanowire structure within an applied counterclockwise rotating field with amplitudes Hx0 = Hy0 = 91 Oe.

Within a suitable counterclockwise rotating field, magneto-optical Kerr effect (MOKE) magnetometry (24, 27, 28) measurement from the position marked by an asterisk in Fig. 1A indicated a switching period of 5 field cycles (Fig. 1C), confirming that the NOT gate, fan-out, and cross-over elements were working correctly.

Of the four logic architecture elements, the cross-over junction is the most challenging to achieve experimentally, and its operation is highly sensitive to the nanowire dimensions. To pass across the cross-over element, a domain wall must expand fully across the junction, an energetically costly process, before being able to propagate further along the output wire. However, domain walls must not be allowed to propagate along the orthogonal wire direction, or else the digital information in the structure will have been altered. In contrast, a domain wall propagating through a fan-out junction will gradually expand from the input wire as the junction widens, before dividing into two separate walls once the output wires are reached.

The integration of all four logic elements was completed in the nanowire network shown in Fig. 2A, consisting of a NOT gate, an AND gate, two fan-out junctions, and one cross-over junction. Our previous work (29) has shown that the switching field of the AND-gate output wire depends on whether neither, one, or both of the input wires contains a domain wall, with the switching field reducing with an increasing number of incident domain walls. In order to achieve logical AND functionality, the AND gate is operated within an elliptical rotating magnetic field with a dc field bias HxDC in the direction of Hx. This is similar to how previous pseudo-AND operations have been achieved in other single-layer magnetic systems (12, 30). The remainder of the magnetic circuit in Fig. 2A was designed to sequentially supply the AND gate with all four possible logical input combinations for a two-input device. However, all wire junctions must be able to tolerate the dc field bias, because this is applied globally.

Fig. 2.

(A) FIB image of a magnetic nanowire network containing one NOT gate, one AND gate, two fan-out junctions, and one cross-over junction. MOKE measurements were made at positions I and IV, indicated by asterisks, and positions II and III denote the inputs to the AND gate. Also indicated are the directions of field components (Hx and Hy) and the sense of field rotation (Rot). (B) MOKE traces describing the operation of the magnetic circuit within a counterclockwise rotating field with amplitudes Hx0 = 75 Oe and Hy0 = 88 Oe and dc offset of HxDC = –5 Oe. Experimental MOKE measurements from positions I and IV of the circuit are shown. Traces II and III are inferred from trace I and show the magnetization state of the AND gate's input wires.

A NOT gate within a feedback loop was used as a signal generator for the rest of the network and should have a 3–field cycle switching period (24, 26). A fan-out element fed domain walls out of the loop and to a second successive fan-out element, where the domain walls were divided into two paths again. MOKE measurement at position I in Fig. 2A indicates a switching period of 3 field cycles (Fig. 2B, trace I), confirming that the NOT gate and sequential fan-out elements were working correctly. Between positions I and II (Fig. 2A), we can infer that domain walls will be delayed by 0.5 field cycles (Fig. 2B, trace II). However, for domain walls from the second fan-out junction to reach position III, they must pass through an additional loop created by the inclusion of the cross-over junction. The magnetization at position III, therefore, will be delayed by 1 field cycle, compared with that at position II (Fig. 2B, trace III). The magnetization direction at positions II and III determines the logical input state of the AND gate. An AND gate has an output value of 1 only when both inputs are 1, and is 0 for all other conditions. The measurement of position IV of the magnetic circuit (Fig. 2B, trace IV) showed this to be the case (using the convention here that a high MOKE signal refers to logical 1), demonstrating that the AND gate was operating correctly together with the other three element types.

Data input. Any useful circuit must be able to receive data from the outside world. Figure 3A shows a circular shift register structure containing eight NOT gates and one fan-out junction, where one of the NOT gates has an enlarged central stub region to lower the magnetization reversal field and make this a data-input element. The stray magnetic field from a current-carrying conductor could be used to write magnetic data directly and locally into the enlarged stub (31, 32). However, in this case we have designed the stub such that field amplitudes required to write data to it lie within the operation range of the other NOT gates and fan-out junction. We can therefore write data by modulating the amplitude of the globally applied rotating magnetic field. The rotating field thus acts simultaneously as a power supply, clock, and serial data channel.

Fig. 3.

(A) FIB image of a 5-bit magnetic shift register consisting of eight NOT gates and one fan-out junction. One NOT gate (NOT′) has an enlarged central stub that is the field-addressable data-input element. The stub narrows to 200 nm over a distance of 350 nm, widens again to 325 nm over 1 μm, remains at 325 nm for another 1 μm, and terminates with an equilateral triangle–shaped end. The directions of field components (Hx and Hy) the sense of field rotation (Rot), and the position of MOKE measurement (asterisk) are indicated. (B to E) Schematic diagrams describing the operation of the data-input element, including the instantaneous field vectors (black arrows), the magnetization directions (white arrows), and the position of domain walls (white dotted line). (F) “Write” field pattern with field amplitudes Hxno-write = 90 Oe, Hxwrite = 138 Oe, and Hy0 = 50 Oe. The 5-bit sequence `11010' is generated during the interval between the dotted lines. (G) MOKE measurements (Hx0 = 90 Oe and Hy0 = 50 Oe) from the shift register in reset configuration (trace I), after applying the “write” field pattern (trace II), and after a 1.85-ms-duration half-sinusoid field pulse of amplitude Hx0 = 243 Oe (trace III).

Figure 3, B to E, shows the operating principle of a data-input element within a clockwise rotating field. From the initial magnetization state (Fig. 3B), a large amplitude field Hxwrite nucleates a domain wall in the element that propagates through the NOT-gate junction and divides into domain walls 1 and 2 along the input/output wires (Fig. 3C). Domain wall 1 is routed around a corner of the same handedness as the applied field rotation and will continue to propagate around the shift register (Fig. 3D). In contrast, domain wall 2 is initially routed around a corner of opposite handedness to the applied field rotation. As the field rotates further, domain wall 2 must reverse its direction and pass back through the NOT gate (Fig. 3D). At the NOT gate, the returning domain wall must again split into two. One part will propagate along what is the output arm of the NOT-gate junction (Fig. 3E), following original domain wall 1 with a half-cycle delay, whereas another part will propagate back along the data-input element to restore the initial magnetization state (Fig. 3E). It is important that this returning domain wall annihilates when it reaches the element end to avoid an oscillation condition. The output of the data-input element from this field sequence with a single nucleation event is, therefore, a pair of domain walls.

The “write” field pattern shown in Fig. 3F was only applied once to fill the shift register with a 5-bit data stream, with only the section between the dotted lines performing data writing (the final field cycle is used to ensure that all domain walls correctly enter the shift register loop). Before the writing process, all domain walls were annihilated by applying a low-amplitude rotating field (26). For writing a single data bit, the amplitude components of one half-cycle of field are Hxwrite = 138 Oe and Hy0 = 50 Oe (directions defined in Fig. 3A), causing the magnetic data-input element to switch as described above. The field conditions for not writing data are Hxno-write = 90 Oe and Hy0 = 50 Oe. MOKE measurement with Hx0 = 90 Oe and Hy0 = 50 Oe of the shift register in its initialized configuration verified that no domain walls were present (Fig. 3G, trace I). After a single application of the “write” field pattern, the shift register contains several two–domain-wall packets that represent a binary data stream of “11010” (Fig. 3G, trace II). Because of the data writing procedure, a low-to-high transition in the MOKE signal corresponds to logical 1, whereas no transition across a full field cycle corresponds to logical 0. This data stream corresponds perfectly to the data stream in the “write” field pattern (Fig. 3F) and confirms the principle of data-input element operation described above. A delay of 1 hour between writing and reading returned the correct bit sequence, demonstrating the intrinsic nonvolatility of the shift register. However, the ultimate room-temperature storage time will far exceed 1 hour, and wire width and thickness can be engineered to ensure that data retention times exceed 10 years. All information within the entire shift register can be removed by the application of a single bulk erase half-sinusoid field pulse of amplitude Hx0 = 243 Oe and 1.85-ms pulse length, immediately filling the shift register with ten domain walls (Fig. 3G, trace III), regardless of the initial magnetization arrangement.

Outlook. We have thus demonstrated the four basis functions (NOT, AND, fan-out, and cross-over) operating simultaneously under the action of a single global applied rotating magnetic field. In principle, any logic circuit can now be implemented, simply by increasingly complex combinations of the four basis functions. All the demonstrations here used a 27-Hz magnetic field frequency to allow easy MOKE measurement and rapid device prototyping. Other initial experiments indicate that NOT gates operate correctly at low-kHz frequencies, with no upper limit observed. Furthermore, previous measurements of domain-wall propagation velocities in excess of 1000 m s–1 (23, 33) suggest propagation delays between wire junctions equal to 0.1 to 2 ns, depending on the design rule size. However, complex gyromagnetic behavior at wire corners (23) and domain-wall pinning at wire junctions are likely to increase these propagation delays and are the subject of ongoing investigation. Domain-wall dynamics are likely to be affected by future miniaturization, but this also remains untested. Additional work is required to integrate either the magnetic data-input element described above or current-carrying wires for data input with the four nanowire logic junctions. Furthermore, we are currently developing magnetoresistive logic read-out elements by using multilayer regions.

One of the most attractive features of domain-wall logic is its great simplicity (Table 1). Logical NAND is achieved in CMOS by using four transistors, whereas domain-wall logic uses two elements (NOT and AND). A logical AND function, usually requiring six CMOS transistors, can be achieved simply by bringing two magnetic nanowires together. Unlike Si CMOS architecture, a domain wall cross-over junction can be achieved in a single plane and without multilevel metallization, which means that in principle, extremely low-cost devices could be produced. Whereas most applications of magnetic logic (and indeed the wider field of spintronics) will involve a hybrid system on a chip that includes silicon-based CMOS, certain applications such as biomedical implants or wearable computing hardware would benefit from the ability to fabricate devices on, for example, flexible polyimide substrates. One could imagine nanowires constructed into three-dimensional (3D) neural networks or hugely dense 3D nonvolatile memories. The ability to supply power, clock, master reset, and serial input with a single externally applied magnetic field, as demonstrated in Fig. 3, is particularly attractive in the 3D case, where signal access is limited. There may also be potential for interfacing domain-wall logic with emerging dilute ferromagnetic semiconductors that allow electrical control and sensing of magnetization (34).

The energy dissipated in each domain-wall logic element must, on very general thermodynamic grounds, be less than 2MsHaV per gate output transition, where Ms is the saturation magnetization of the magnetic material (800 electromagnetic units cm–3 for Permalloy), Ha is the amplitude of the externally applied magnetic field, and V is the volume of magnetic material switching in the gate and its output nanowire. For the devices described here, typical values for the energy per operation are 10–5 pJ (2000kBT at room temperature, where kB is Boltzmann's constant and T is temperature), compared with the typical energy per gate of CMOS of 10–2 pJ for a 200-nm minimum feature size (35). This could allow large 3D domain-wall logic circuits to operate without overheating. However, domain-wall logic will not necessarily be a low–power-consumption technology, because there are considerable inefficiencies in generating magnetic fields. Absolute power consumption might be kept low by using small-area (few hundred μm2) domain wall–CMOS hybrid devices, with strip lines for local field generation. However, domain-wall propagation by spin transfer (3638) may ultimately overcome these inefficiencies altogether.

The future scaling performance of domain-wall logic depends on the interplay between thermodynamic stability and the required magnitude of the externally applied field. Both of these depend on F, the width of the nanowires that form the logic elements. If the width and thickness of the nanowires are scaled together, then the shape anisotropy remains unchanged. To first order, the strength of the externally applied magnetic field required to overcome fabricational edge roughness and discontinuities at the logic elements therefore remains constant. In this case, the energy per gate transition scales with the volume of magnetic material, proportional to F3. Thus, at F = 70 nm, a 1.8-nm-thick magnetic logic device should dissipate 3 × 10–7 pJ (70kBT at room temperature), which is the lower limit for thermodynamic stability. For further reductions in F, the device thickness should be increased by scaling by F–1/2 in order to keep the energy per gate transition unchanged. This will cause shape anisotropy to increase, and hence the required externally applied field for domain-wall propagation through wires and the structural discontinuities associated with wire junctions will increase as well. As with MRAM, the ultimate limit of scaling will be when the required externally applied field becomes impracticably large (39). What is not currently known is how well defined some of the fine features in the logic elements, such as the point in the center of the NOT gate, have to remain as F is scaled down. This will determine the relationship between F and the required resolution of the lithography, and hence the relationship with Moore's law. We would expect that fine definition should become less important as F is reduced, because the exchange interaction will increasingly average the local magnetization response.

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