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Organic Nonvolatile Memory Transistors for Flexible Sensor Arrays

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Science  11 Dec 2009:
Vol. 326, Issue 5959, pp. 1516-1519
DOI: 10.1126/science.1179963

Abstract

Using organic transistors with a floating gate embedded in hybrid dielectrics that comprise a 2-nanometer-thick molecular self-assembled monolayer and a 4-nanometer-thick plasma-grown metal oxide, we have realized nonvolatile memory arrays on flexible plastic substrates. The small thickness of the dielectrics allows very small program and erase voltages (≤6 volts) to produce a large, nonvolatile, reversible threshold-voltage shift. The transistors endure more than 1000 program and erase cycles, which is within two orders of magnitude of silicon-based floating-gate transistors widely employed in flash memory. By integrating a flexible array of organic floating-gate transistors with a pressure-sensitive rubber sheet, we have realized a sensor matrix that detects the spatial distribution of applied mechanical pressure and stores the analog sensor input as a two-dimensional image over long periods of time.

Electronic devices are traditionally fabricated using inorganic semiconductors, rigid substrates, and high-temperature manufacturing methods. In contrast, organic semiconductors can be processed at low temperatures and on large-area polymeric substrates. This has allowed for the development of a variety of electronic devices on flexible plastic substrates, including solar cells (1), light-emitting diode displays (2), field-effect transistors (3), transponders (4), sensors (5), actuators (6), and nonvolatile memory transistors (711). Nonvolatile memory transistors are potentially useful to individualize radio-frequency transponders or to store data obtained by large-area sensor arrays for later read-out. Most of the organic memory transistors reported to date exploit the electric field–induced remnant polarization in ferroelectric polymer films (711). A considerable limitation of ferroelectric polymer memory transistors is that the coercive field required to reverse the macroscopic polarization increases with decreasing film thickness (12), which makes it difficult to obtain a large enough memory window with program and erase voltages below about 20 V. Also, due to the substantial surface roughness of the ferroelectric polymer films, the carrier field-effect mobility in these transistors is usually quite low (<0.1 cm2/Vs).

A floating-gate transistor is a field-effect transistor with two gate electrodes. In addition to the control gate, similar to that in a regular transistor, it has a floating gate embedded in the gate dielectric. When the dielectric is thin enough, electronic charge can be brought onto the floating gate by quantum tunneling or thermal emission when a large enough program voltage is applied between the control gate and the source contact. Charging the floating gate changes the transistor’s threshold voltage, because the charge on the floating gate partially screens the electric field between the control gate and the semiconductor. This threshold voltage shift can be detected by measuring the drain current at a certain gate-source voltage. Because the floating gate is completely isolated by the dielectric, charge stored on the floating gate remains there without the need for any applied voltage (nonvolatile memory). To erase the memory, a voltage of opposite polarity is applied, discharging the floating gate through the dielectric.

In silicon-based floating-gate transistors, the dielectric is a silicon dioxide layer with a thickness of a few nanometers. The exact thickness is a compromise between the voltage required to bring enough charge onto the floating gate and the charge leakage from the floating gate, which sets an upper limit on the retention time. Silicon-based floating-gate transistors typically have program and erase voltages of 10 to 20 V (13, 14) and retention times of several years. Because the defect density in the thin dielectric increases with every program and erase operation, the endurance is usually limited to ~106 program and erase cycles (14).

Although silicon floating-gate transistors are excellent for high-density data storage, flexible organic floating-gate transistors are potentially useful for large-area sensors and actuators with integrated nonvolatile memory capability. There are very few reports of organic floating-gate transistors, most of which use rigid substrates, thick dielectrics (10 to 50 nm) and large program and erase voltages (15 to 50 V), and none of which have demonstrated integration of these transistors into memory arrays (1518). The main challenge in reducing the program and erase voltages and in demonstrating high yield and sufficient uniformity in large-area memory arrays on flexible plastic substrates is to develop a dielectric that can be prepared below the glass transition temperature of plastic film (<150°C) and which combines small film thickness with good reproducibility and small defect density. By taking advantage of the excellent properties of a low-temperature hybrid dielectric based on a thin metal oxide and a self-assembled monolayer (SAM), we have developed flexible floating-gate transistors with small program and erase voltages (–6 V to +3 V). Figure 1A shows a photograph of a plastic sheet with 676 organic floating-gate transistors arranged in a 26 by 26 array on a 125-μm-thick plastic film. The schematic device cross section is shown in Fig. 1B; the fabrication process is outlined in the Supporting Online Material. The two dielectrics that isolate the floating gate from the control gate and the organic semiconductor are a combination of a thin aluminum oxide (AlOx) layer grown in an oxygen plasma at room temperature and an alkyl-phosphonic acid SAM prepared from solution at room temperature, with a total thickness of about 6 nm and a capacitance of 0.6 to 0.65 μF/cm2 (1922). The semiconductor is a thin layer of vacuum-deposited pentacene.

Fig. 1

(A) Photograph of an organic floating-gate transistor sheet comprising 26 by 26 memory cells. The array has an effective area of 50 by 50 mm2. The inset shows a magnified image of the array. (B) Schematic cross section of the floating-gate transistors. The substrate is flexible PEN. The control and floating gates are 20-nm-thick layers of evaporated aluminum. The top and bottom dielectrics are each a combination of a 4-nm-thick layer of AlOx and a 2-nm-thick SAM. The organic semiconductor is a 50-nm-thick layer of pentacene, and the source and drain contacts are 50-nm-thick layers of evaporated gold. (C) Cross-sectional TEM images of a flexible floating-gate transistor. The specimen was prepared using a focused ion beam and imaged by TEM (300 kV).

Figure 1C shows a cross-sectional electron microscopy (EM) image of a completed device. The specimen was prepared using a focused ion beam (FIB) (FB-2100, Hitachi High-Technologies Corp., Tokyo, Japan) and imaged by transmission electron microscopy (TEM) (HF-3300 Cold-FE TEM, 300 kV, Hitachi High-Technologies Corp.). The control gate, the floating gate, and the two dielectric layers can be clearly distinguished in the TEM image. Perhaps most notably, the 2-nm-thick organic SAM of the bottom dielectric that separates the control gate from the floating gate is clearly resolved. The TEM image confirms the structure of the organic floating-gate transistors.

To characterize the electric current through the dielectrics during program and erase operations, floating-gate capacitors were prepared without the semiconductor (Fig. 2A). Figure 2B shows that when the voltage between the control gate and the top contact increases, the current also increases, reaching 0.5 mA/cm2 at 6 V. This measurement was repeated 100 times without any changes in the current-voltage curves, showing that the dielectric can sustain this current. Beyond 6.3 V, however, an irreversible increase in current was observed, indicating damage to the dielectric (fig. S3A).

Fig. 2

Static electrical performance of the floating-gate memory devices. (A) Photograph of a floating-gate capacitor used for characterizing the voltage-dependent current through the AlOx/SAM dielectrics. (B) Current through the AlOx/SAM dielectrics as a function of applied voltage. Up to 6 V, the current does not cause irreversible changes in the dielectrics. (C) Photograph of a pentacene floating-gate memory transistor. (D) Drain current as a function of the voltage applied between control gate and source contact. When the applied voltages are –6 V and +3 V, the floating gate is charged and discharged, causing a threshold-voltage shift and hysteresis in the current-voltage characteristics. (E) Read-out operation performed on a floating gate transistor after programming and after erasing for 1 s. The threshold-voltage shift induced by the program and erase operations is clearly observed. (F) Gate current of a floating-gate transistor measured during read-out. For read-out voltages up to ±2 V, the gate current reaches about 100 pA.

Figure 2C shows a photograph of a pentacene floating-gate memory transistor. Initially, the threshold voltage (Vth) is between +1 and +2 V (Figs. 2 and 3). For programming, a voltage of –6 V is applied between the control gate and the source contact. This creates a gate current of 1 μA (fig. S3B), which charges the floating gate and shifts Vth to –1 V. To erase, a voltage of +3 V is applied to discharge the floating gate and recover the initial threshold voltage. Cycling the gate-source voltage between +3 V and –6 V produces the hysteresis seen in Fig. 2D. The exact Vth shift depends on the voltage and duration of the program pulse (Fig. 3, A and B, and figs. S4 and S5). To read the stored information, Vth is determined, for example, by measuring the drain current as a function of gate-source voltage. Figure 2E shows the result of two read-out operations, one on a transistor programmed at –6 V, the other on a transistor erased at +3 V. The threshold voltage window and the device-to-device uniformity (fig. S6) are sufficient for unambiguous read-out. Figure 2F shows that if read-out is performed with a gate-source voltage of ±2 V, the gate current reaches 100 pA. This causes a small portion of the stored charge to be lost and Vth to shift slightly during each read-out operation (destructive read-out) (fig. S7, A and B). In contrast, if read-out is performed with a gate-source voltage of 0 V, there is no charge loss and no Vth shift (nondestructive read-out) (fig. S7C).

Fig. 3

Threshold voltage of organic floating-gate transistors. (A) Threshold-voltage shift as a function of program voltage. The program voltage is applied for 1 s. At the maximum program voltage of –6 V, a threshold-voltage shift of about 2.5 V is obtained. The threshold voltage after erasing with +3 V is independent of the program voltage. (B) Threshold-voltage shift as a function of the duration of the program pulse. The program voltage is –6 V. (C) Endurance of the memory transistors. The threshold-voltage window is greater than 2 V after 103 program and erase (–6 to +3 V) cycles and greater than 1 V after 104 cycles. (D) Retention characteristics of the memory transistors. The threshold voltage window is greater than 2 V after 103 s and greater than 1 V after 104 s. For each data point, the threshold voltage was obtained by measuring the complete transfer characteristics [sweeping gate-source voltage (VGS) from +2 to –2 V; drain-source voltage (VDS) = –1 V].

Modern silicon-based flash memory is typically rated for 106 program and erase cycles (14), after which the memory characteristics degrade. To evaluate the endurance of the organic memory transistors, a device was subjected to 105 program and erase cycles (–6 V to +3 V, 1 Hz). The results in Fig. 3C and in fig. S8 show that the threshold voltage window is constant at 2 V up to 103 cycles. Beyond that, the positive threshold voltage shift during the erase operation becomes smaller, so the initial threshold voltage of +1 V is no longer recovered and the threshold voltage window becomes smaller. Nonetheless, after 104 cycles, the threshold voltage window is still 1 V, sufficient for unambiguous read-out. After 105 cycles, the threshold voltage window is 0.5 V. Interestingly, the initial threshold voltage of +1 V can be recovered by annealing the transistors at 140°C in dry nitrogen, which suggests that the endurance is limited not by irreversible structural damage but by reversible carrier trapping.

Unlike dynamic random access memory (DRAM), nonvolatile memories retain information in the absence of external voltages. In floating-gate transistors, this requires that the charge on the floating gate is prevented from leaking away through the dielectric. Data retention experiments on an individual pentacene device (shown in Fig. 3D) suggest that the retention time is only a few hours (threshold voltage window is 1.1 V after 3 hours, 0.6 V after 12 hours). However, most of the charge loss in this case occurred during read-out. To improve retention, we have therefore designed and fabricated a two-transistor memory cell in which an access transistor (with control gate) and a read-out transistor (without control gate) share a floating gate with an area of 400 by 1000 μm2 (Fig. 4A). Read-out is performed with a drain-source voltage of –1 V applied to the read-out transistor for 0.1 s or less, with no voltage applied on the control gate. This resulted in a significant improvement in retention time: After 3 hours, the read-current ratio is less than 2 for the one-transistor cell, but 2 × 102 for the two-transistor cell. After 12 hours, the two-transistor cell still has a usably large read-current ratio of 102 (Fig. 4B).

Fig. 4

Flexible pressure-sensor array. (A) Schematic and photograph of a two-transistor (2T) memory cell in which an access transistor (TA) and a read-out transistor (TR) share a large floating gate. (B) Retention characteristics of a 2T cell in comparison with that of a 1T cell. The read current (IRead) is the drain current of TR measured with a drain-source voltage (VRead) of –1 V. IRead depends on the threshold voltage of the transistors and thus on the amount of charge on the floating gate. (C) Circuit schematic of the sensor. Lines marked AL are the access lines used to apply a drain-source voltage of –2 V to the access transistors during program and erase operations. Lines marked RL are the read lines. The control gates of all access transistors are connected to the bottom surface of the pressure-sensitive rubber sheet. (D) Photograph of the three individual sheets before lamination. Bottom, 125-μm-thick PEN sheet with 676 2T memory cells; center, 500-μm-thick pressure-sensitive rubber sheet; top, 125-μm-thick PEN sheet with copper electrode. (E) Demonstration of the sensor array. The spatial distribution of mechanical pressure applied using two different objects is stored in the organic floating-gate transistors and can be retrieved even after the pressure and voltages have been removed.

To demonstrate the potential of organic floating-gate transistors and the two-transistor memory cell design, we fabricated a large-area flexible sensor that measures the spatial distribution of mechanical pressure applied to it and retains this data for more than 12 hours after the pressure and voltages have been removed. The sensor was fabricated by laminating three sheets: a polyethylene naphthalate (PEN) sheet with 676 two-transistor memory cells arranged in a 26 by 26 array, a pressure-sensitive rubber sheet, and a PEN sheet with a copper electrode. The circuit schematic is shown in Fig. 4C, a photograph of the three individual sheets before lamination is shown in Fig. 4D, photographs of the memory array are shown in fig. S10A, and a cross section of the laminated stack is shown in fig. S10B. The control gates of all 676 memory cells are connected to the bottom surface of the rubber sheet, and the top surface of the rubber sheet is in contact with the copper electrode. When mechanical pressure is applied to the rubber sheet, the electrical resistance between the rubber’s top and bottom surfaces decreases (fig. S10C). By applying a program voltage to the copper electrode and an access voltage to all memory cells, the copper electrode supplies the program voltage to the floating-gate transistors in those positions where pressure is applied, and the pressure distribution is stored in the memory array.

Figure 4E shows a demonstration of the sensor. Pressure was applied using two different objects: a roll of tape and two fingers. The stored information was read out after 20 min and again after 12 hours with a multichannel drive system. As can be seen, the contrast between the programmed cells and the background deteriorates over time due to charge loss (Fig. 4B), but even 12 hours after removing the mechanical pressure and the electric voltages, the stored information showing the spatial distribution of the applied pressure was still successfully recovered.

Supporting Online Material

www.sciencemag.org/cgi/content/full/326/5959/1516/DC1

Materials and Methods

SOM Text

Figs. S1 to S10

References and Notes

  1. This study was partially supported by Core Research for Evolutional Science and Technology, Japan Science and Technology Agency (JST/CREST), Global Centers of Excellence (GCOE, Secure-Life Electronics, University of Tokyo), and the Special Coordination Funds for Promoting and Technology. We thank H. Matsumoto and Y. Kuroda (Hitachi High-Technologies Corp.) for the process using FIB and imaging by TEM, H. Takagi (GENESIS Co., Ltd.) for designing the multichannel sensor driving system, and Daisankasei Co., Ltd. for high-purity parylene (diX-SR). We also thank T. Furukawa (Tokyo University of Science) and R. Koeppe (Johannes Kepler University Linz) for valuable discussion. S.B. thanks the Austrian Science Funds for financial support.
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