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Wafer-Scale Graphene Integrated Circuit

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Science  10 Jun 2011:
Vol. 332, Issue 6035, pp. 1294-1297
DOI: 10.1126/science.1204428

Abstract

A wafer-scale graphene circuit was demonstrated in which all circuit components, including graphene field-effect transistor and inductors, were monolithically integrated on a single silicon carbide wafer. The integrated circuit operates as a broadband radio-frequency mixer at frequencies up to 10 gigahertz. These graphene circuits exhibit outstanding thermal stability with little reduction in performance (less than 1 decibel) between 300 and 400 kelvin. These results open up possibilities of achieving practical graphene technology with more complex functionality and performance.

Graphene, a layer of carbon atoms arranged in a hexagonal lattice, is a promising candidate for future high-speed electronics and radio-frequency (RF) applications (14) because of its high carrier mobility and saturation velocity (5). The planar structure and the feasibility of large-area graphene synthesis facilitate the adoption of top-down device fabrication techniques. Graphene transistors with intrinsic cut-off frequencies beyond 100 GHz have been recently achieved by several groups using graphene films synthesized by various methods, including epitaxial growth on SiC (6, 7), chemical vapor deposition (CVD) on Cu (8), and mechanical exfoliation (9, 10). The monolithic integration of transistors with interconnects and other components is an essential requirement for any semiconductor material to achieve a widespread technological impact. Previous attempts to make circuits based on graphene have used an individual graphene transistor connected to external passive elements (1113). Such heterogeneous circuitry inevitably results in degraded performance dominated by interconnects and parasitics rather than the intrinsic properties of graphene device. For example, Wang et al. demonstrated an RF frequency mixer operating at a few tens of megahertz based on a single graphene transistor (12).

Despite recent progress in graphene synthesis and device performance, scalable integration of graphene into a practical circuit remains challenging. The key difficulties stem from the distinct materials properties of graphene with respect to those of conventional semiconductors, such as a different ohmic contact formation mechanism (14), poor adhesion with metals and oxides (15, 16), and its vulnerability to damage in plasma processing. Thus, bridging the technological gap between a single device and a practical graphene circuit on the wafer scale requires innovative integration processes and circuit designs. Here, we describe wafer-scalable processes that have been developed to fabricate arrays of graphene analog circuits, each consisting of one graphene transistor and two inductors, all compactly integrated on a single SiC substrate. The entire integrated circuit (IC), including the contact pads, is less than 1 mm2, and successful integration is verified by operating it as an RF mixer at a designated gigahertz frequency range.

The previously demonstrated frequency multipliers and mixers using graphene field-effect transistors (GFETs) were based on the ambipolar transport characteristics of CVD and exfoliated graphene (1113). The mixer circuit design exploits a general gate-driven and drain-driven current modulation behavior in GFETs that can be used in both ambipolar and unipolar devices. Mixers are electrical circuits used for frequency conversion and are critical components in modern RF communication systems. Two high-frequency signals, an RF signal at a frequency fRF and a local oscillator (LO) signal at a frequency fLO, are applied to the gate and the drain of the GFET through port P1 and port P4, respectively (Fig. 1A). The graphene transistor is modulated by both signals and produces a drain current that contains the mixed frequencies, the sum (fRF + fLO), and the difference (fRF fLO, the intermediate frequency fIF) of the input frequencies. The integrated inductors complement the graphene FET to form an integrated RF mixer. Inductor L1 resonates out the parasitic capacitances from the input RF pad and the gate of the graphene FET, while inductor L2 provides an input match to the LO signal and acts as a low-pass filter between the drain of the FET and the output port P3. In practice (e.g., in a radio receiver application), frequencies of the RF and LO input signals differ by only a small amount, and the output signal component of interest is fIF.

Fig. 1

(A) Circuit diagram of a four-port graphene RF frequency mixer. The scope of the graphene IC is confined by the dashed box. The hexagonal shape represents a graphene FET. (B) Schematic exploded illustration of a graphene mixer circuit. The critical design aspects include a top-gated graphene transistor and two inductors connected to the gate and the drain of the GFET. Three distinct metals layers of the graphene IC are represented by M1, M2, and M3. A layer of 120-nm-thick SiO2 is used as the isolation spacer to electrically separate the inductors (M3) from the underlying interconnects (M1 and M2).

Graphene circuits were fabricated on a semi-insulating SiC wafer. A two- or three-layer graphene film was epitaxially grown on the Si face of the SiC substrate at temperatures above 1400°C (1719), as confirmed by Raman spectroscopy and optical absorption measurements (see fig. S1 in the supporting online material). Fabrication of the graphene IC began with top-gated, two-finger graphene FETs (Fig. 2A), followed by integration with on-chip inductors. To form the active channel of the transistor, we spin-coated the graphene-SiC wafer with a layer of 140-nm-thick PMMA [poly(methyl methacrylate)] followed by a layer of 20-nm-thick HSQ (hydrogen silsesquioxane). The FET channel was defined by e-beam lithography (EBL); the surrounding graphene was removed by an oxygen plasma with the exposed HSQ film as the protecting mask. The HSQ-PMMA stack over the channel region was subsequently removed by acetone.

Fig. 2

Images of graphene ICs. (A) Scanning electron image of a top-gated, dual-channel graphene transistor used in the mixer IC. The gate length is 550 nm and the total channel width, including both channels, is 30 μm. Scale bar, 2 μm. (B) Optical image of a completed graphene mixer including contact pads. The gound-signal-ground configuration is implemented for the probe pads suitable for direct RF testing. Scale bar, 100 μm.

The removal of graphene film on SiC outside of the active channel region was critical to achieve good adhesion of thick metals in the subsequent deposition processes. The ohmic source and drain contacts, contact pads, and gate electrode were all made of the same metal stack of 20-nm Pd, 40-nm Au. The gate length was 550 nm and the distance between source and drain contacts was 600 nm. The gate dielectric was deposited by evaporating two 2-nm layers of Al metal onto the graphene channel that were then oxidized at elevated temperatures (~ 120°C) in air to form a seed layer for the subsequent deposition of Al2O3 (20 nm) by atomic layer deposition (14). The capacitance of the resulting gate dielectric stack was ~2. 5 × 10−7 F/cm2.

Inductors were defined by EBL and formed by depositing 1-μm-thick Al metal. A layer of 120-nm-thick SiO2, deposited by e-beam evaporation, was used to isolate the inductor loops from the underlying metal interconnects. The inductor had a value of 5.2 nH, a self-resonant frequency of ~10 GHz, and quality factor (Q) of 5, as measured on a stand-alone test site. The inductance was designed to achieve a target operation frequency of 5 GHz for the mixer circuit, and the quality factor of 5 is appropriate for broadband operation. Figure 2B shows an image of the completed graphene circuit, including the inductors, GFET, and contact pads. The layout of the entire die, containing arrays of graphene ICs used as monitor devices and other testing components, is shown in fig. S3.

Figure 3A shows the current Id and transconductance gm as a function of gate voltage Vg of a typical graphene transistor with a gate length of 550 nm at drain voltage Vd = 1.6 V measured at room temperature. Within the gate voltage range studied here, the GFETs always exhibited dominant n-type transport (6, 17, 19), which differs from the ambipolar characteristics typically observed in CVD and exfoliated graphene. The output characteristics of the GFET (Fig. 3B) exhibited a nearly linear Id-Vd dependence for all gate voltages up to a drain voltage of 1.6 V. These triode-like output characteristics resulted in a device transconductance that increased with rising Vd. At a drain bias of 1.6 V, a current density above 2 mA/μm and a transconductance of 80 μS/μm were achieved. The measured current density was enhanced by the high intrinsic doping level (up to 1013 cm−2) of graphene. Figure 3C shows the distribution of the peak transconductance of 13 GFETs fabricated on the same wafer, with most devices ranging between 60 and 80 μS/μm. The contact resistance of the graphene transistor, which included the source and drain contacts, was about 600 ohm·μm. On the basis of the measured dc transconductance and gate capacitance, the intrinsic cut-off frequency of the GFET is estimated to be ~9 GHz for a gate length of 550 nm and drain bias of 1.6 V.

Fig. 3

(A) The drain current Id of a 550-nm–gate-length graphene FET as a function of gate voltage Vg at a drain bias of 1.6 V with the source electrode grounded. The current shown was normalized with respect to the total channel width. The device conductance gm is shown on the right axis. (B) The measured drain current Id as a function of drain bias of the graphene FET for various top-gate voltages. (C) Distribution of peak gm of graphene FETs, all of the same gate length of 550 nm and fabricated on the same wafer.

Unlike conventional mixers that are typically realized by applying LO and RF signals to a nonlinear device, such as a Schottky-barrier diode, the mixer IC discussed here uses channel resistance modulation of the graphene FET to achieve frequency mixing. The drain current exhibits a nearly linear dependence with respect to gate and drain voltages (Fig. 3, A and B) and can be expressed, to the first-order approximation, by IdA(B+gmVg)Vd, where A and B are constants. The frequency mixing becomes evident in view of the product term of Vg and Vd. Because the output signal is proportional to the drain current modulation, the power of output signal fIF is proportional to the product of the transconductance gm=(dIddVg) and the output conductance gd=(dIddVd). Although current saturation in the Id-Vd curves, which corresponding to a small gd, is a desirable feature for RF and analog applications in general, it remains challenging to achieve well-behaved current saturation in graphene FETs, especially for small gate lengths (20, 21). Most graphene devices exhibit a triode-like Id-Vd behavior such as the one shown in Fig. 3B. By using the finite conductance gd of graphene transistors to realize mixing, the output signal is linearly proportional to both gate and drain input signals. This configuration has been previously used with GaAs FETs operating in the linear region (22), achieving a superior linearity compared to mixers that use diodes or FETs operating in saturation mode.

Figure 4A displays the output frequency spectrum of the graphene mixer with input signals fRF = 3.8 GHz and fLO = 4 GHz and a drain bias of 2 V. The frequency mixing function was visible as two tones observed at frequencies fIF of 200 MHz and fRF + fLO of 7.8 GHz. The higher-frequency tone was attenuated by the drain inductor and hence showed lower amplitude. The power of signal fIF was proportional to that of the input RF signal up to PRF = 12 dBm for an LO signal as high as PLO = 20 dBm (fig. S5); this high level of linearity is expected from the mixer configuration as described above. The conversion loss, defined as the power ratio of the IF signal PIF and the input RF signal PRF, is about −27 dB. Figure 4B shows the dependence of conversion loss of the mixer on the LO frequency while maintaining fIF at 200 MHz. The performance of this graphene mixer peaked around fLO ~ 4.5 GHz, which is in good agreement with the target frequency of 5 GHz. These results not only validate the proper function of the graphene circuit as an RF mixer, but also demonstrate successful integration and operation of an active graphene device coupled with supporting components on a single chip.

Fig. 4

(A) A snapshot of output spectrum, between 0 and 10 GHz, of the mixer taken from the spectrum analyzer with fRF = 3.8 GHz and fLO = 4 GHz. Each x and y division corresponds to 1 GHz and 10 dBm, respectively. The graphene FET was biased at a drain bias of 2 V and a gate voltage of −2 V. The input RF power was adjusted to 0 dBm, so that the output spectrum power measured the actual loss (gain) with respect to the RF input. The frequency mixing was visible with two peaks observed at frequencies of 200 MHz and 7.8 GHz with signal power of −27 and −52 dBm, respectively. (B) Measured conversion loss of the graphene frequency mixer as a function of LO frequency. The conversion loss was normalized to the value at fLO = 4 GHz. The solid line is a guide to the eye. (C) Conversion loss of the mixer measured as a function of Vg of the graphene FET, normalized to the value at Vg = −3 V. (D) Distribution of the conversion loss of seven working graphene mixer ICs, all fabricated on the same wafer. The conversion loss was normalized to their average value. (E) Temperature dependence of conversion loss of the graphene mixer between 300 and 400 K measured at Vd = 1 V and Vg = −1 V. The conversion loss was normalized to the value at 300 K, showing performance degradation less than 1 dB in this temperature range. The solid line is a guide to the eye.

Figure 4C shows the dependence of conversion loss of the mixer on dc gate voltage, revealing a trend that qualitatively follows the variation of transconductance gm as a function of Vg (Fig. 3A). The strong correlation between the conversion loss and gm shows that performance of the graphene mixer was determined by the properties of GFET itself and not by parasitic signal transmission. The conversion gain can be enhanced by further improving gm, e.g., by adopting a thinner oxide and a shorter channel length. As the drain voltage increases from 0.3 to 2 V, the conversion loss is improved by about +3 dB, in agreement with the increasing gm with Vd (Fig. 3B). The conversion loss of all mixers fabricated on the same wafer and measured at identical dc bias conditions varied within ±2 dB (Fig. 4D). To evaluate temperature response of these graphene ICs, we measured the mixer performance as a function of temperature up to T = 400 K. In conventional semiconductor devices, the performance is usually severely degraded as T increases, and additional feedback circuitry is required to minimize the thermal sensitivity. In contrast, the conversion loss of the graphene mixer exhibits little, if any, temperature dependence with a variation below 1 dB in this wide range from 300 to 400 K (Fig. 4E). The absence of strong temperature dependence of graphene ICs is attributed to a degenerate doping level in these GFETs and a nearly T-independent scattering mechanism associated with optical phonons at high biases (8, 20, 23).

The integration techniques and operating principles of graphene circuits described here can be applied to CVD graphene and are also compatible with optical lithography for reduced cost and enhanced throughput. The fabricated graphene IC achieved a 27-dB conversion loss at 4 GHz. In comparison, previously reported graphene-based mixers operated at 10 MHz with a 40-dB conversion loss (14), and a commercially available GaAs-based mixer achieves 7-dB conversion loss at 1.95 GHz (24). In addition, the operation of these mixers required external passive components, whereas the graphene mixer presented here was integrated. The use of thin high-k dielectrics (e.g., 2 nm HfO2) or highly scaled gate lengths (e.g., 40 nm) (8) could improve the FET transconductance by a factor of 10, which would lead to an enhancement of more than 20 dB in conversion gain for the graphene mixer. Moreover, such FET improvement in combination with the integration scheme described here would also enable other graphene-based circuits, such as amplifiers and oscillators, and their use in wireless communication systems.

Supporting Online Material

www.sciencemag.org/cgi/content/full/332/6035/1294/DC1

Materials and Methods

Figs. S1 to S6

References

References and Notes

  1. Acknowledgments: We are grateful to B. Ek and J. Bucchignano for technical assistance and to D. K. Gaskill for providing some epitaxial graphene wafers for testing. We also acknowledge discussions with F. Xia, T. Mcardle, H.-Y. Chiu, and C. Y. Sung. We thank Defense Advanced Research Projects Agency (DARPA) for financial support through the CERA program (contract FA8650-08-C-7838). The views, opinions, and/or findings contained here are those of the authors and do not represent the official views or policies of DARPA or the Department of Defense.
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