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End-bonded contacts for carbon nanotube transistors with low, size-independent resistance

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Science  02 Oct 2015:
Vol. 350, Issue 6256, pp. 68-72
DOI: 10.1126/science.aac8006

Making better small contacts

Semiconducting single-walled carbon nanotubes have potential size and conductivity advantages over silicon for making smaller transistors. However, as metal electrical contacts decrease in size, the associated resistance increases to impractical values. Cao et al. reacted molybdenum films with semiconducting carbon nanotubes to create a carbide contact. The resistance of these contacts remained low even for 10-nm-scale contacts.

Science, this issue p. 68

Abstract

Moving beyond the limits of silicon transistors requires both a high-performance channel and high-quality electrical contacts. Carbon nanotubes provide high-performance channels below 10 nanometers, but as with silicon, the increase in contact resistance with decreasing size becomes a major performance roadblock. We report a single-walled carbon nanotube (SWNT) transistor technology with an end-bonded contact scheme that leads to size-independent contact resistance to overcome the scaling limits of conventional side-bonded or planar contact schemes. A high-performance SWNT transistor was fabricated with a sub–10-nanometer contact length, showing a device resistance below 36 kilohms and on-current above 15 microampere per tube. The p-type end-bonded contact, formed through the reaction of molybdenum with the SWNT to form carbide, also exhibited no Schottky barrier. This strategy promises high-performance SWNT transistors, enabling future ultimately scaled device technologies.

After decades of rapidly increasing computer performance, microprocessor clock frequencies have stalled at ~3 to 5 GHz since the early 2000s, as silicon (Si) metal-oxide-semiconductor field-effect transistors (MOSFETs) approach their physical limits (13). Two key issues are making high-performance but low-power devices with ultrashort gate pitch (the summary of channel length Lch, the distance between the source and drain electrodes, and the contact length Lc, the length of these contacts)—that is, less than 30 to 40 nm—and lowering the contact resistance between the electrodes and the channel. The problems are interrelated, in that contact resistance increases with decreasing Lc for Si and especially for III-V semiconductors such as GaAs (2, 4). Semiconducting single-walled carbon nanotubes (SWNTs) potentially offer the optimal performance as the channel material for ultrascaled FETs (57). The SWNT saturation velocity is several times higher than that of Si, and the intrinsic thinness (~1 nm in diameter) of SWNTs provides the superior electrostatic control needed for devices with ultrashort Lch (6). Indeed, SWNT transistors with 9 nm Lch outperform the best Si MOSFETs with similar Lch (8, 9), and SWNT transistors with advanced self-aligned “gate-all-around” geometry have been fabricated (10, 11) and integrated into complex functional integrated circuits (12, 13).

However, as is the case with Si and III-V semiconductors, a key obstacle to ultrascaled SWNT transistor technology is forming low-resistance and scalable contacts. The total contact resistance 2Rc dominates the performance of scaled devices as the channel transport becomes ballistic. Early SWNT transistors were plagued by poor electrical properties of the metal contacts (14, 15). In a major advance, Javey et al. achieved low-resistance barrier-free p-type electrical contacts to SWNT using palladium (Pd) (16). As in earlier work, the Pd metal was deposited on top of the SWNT to form so-called side-bonded contacts, in which electrons are injected along the length of the tube-metal interface (15, 17). However, with such a contact scheme, 2Rc is low only for large-area contacts, reflecting the weak Pd-SWNT coupling, and the resistance 2Rc increases rapidly as the contact area shrinks (1820). [The weak metal-SWNT coupling is not well understood and might reflect the nonideal wetting of metals on a curved nanotube surface, or the partial coverage of nanotube surface by insulating impurities such as amorphous carbon (C)]. The contact area is proportional to Lc measured along the SWNT direction. Previous experiments indicate that 2Rc will increase from ~5 kilohm for long contacts (Lc > 200 nm) to ~65 kilohm at Lc of 9 nm (21), and to much higher values for even smaller contacts, which is unacceptably large for logic transistors beyond the 2020 time frame (22).

Here, we report a contact scheme that allows scaling the contacts to 10 nm and beyond without increasing 2Rc. An end-bonded contact, in which the SWNT channel abruptly ends at the metal electrodes, is formed through a solid-state reaction between the nanotube and deposited Mo electrodes. Although the carrier injection is limited to an interface of ~2 nm2 in size, 2Rc was remarkably low, down to 25 to 35 kilohm. No barrier was observed for hole transport, and scaling Lc from 300 nm to below 10 nm did not change the contact resistance; whereas in conventional side-bonded contacts to nanotubes or planar contacts in Si MOSFETs, 2Rc shows a characteristic dependence on Lc. Using this end-bonded contact scheme, we successfully demonstrate a p-channel SWNT transistor with an average contact length of merely 9 nm that exhibits on-state resistance below 36 kilohm, an on/off current ratio above 104, an on-current above 15 μA, and a zero Schottky barrier at contacts.

Ab initio calculations suggest that SWNTs could form good electrical contacts to metals in the end-bonded geometry in which an open tip of the nanotube is directly coupled to metal electrodes through strong covalent bonds (2325). However, it is very difficult to realize such a structure in experiment. Zhang et al. reported the fabrication of SWNT-metal heterostructures through the solid-state carbide formation reaction, in which the C-C bond cleavage and the C-metal bond formation were completed simultaneously (26). The atomically abrupt metal-nanotube junctions have been characterized by means of transmission electron microscopy (TEM) for metals including titanium (Ti) and niobium (Nb) (26), as well as tungsten (W), iron (Fe), and chromium (Cr) (27, 28). However, their successful adoption in transistors as reliable low-resistance contacts has not yet been demonstrated because of integration challenges. The best attempt to date used Ti (29), but Ti is problematic because its low work function leads to a Schottky barrier (29, 30), and destructive reactions with the gate oxide occur at the carbide formation temperature (31). Fifteen metals are known to form stable carbide phases (32), and among these, W, molybdenum (Mo), and Fe exhibit the highest electronegativity or work function and thus have the strongest tendency to form carbides rather than oxides. Among these three candidates, WC requires formation temperature well above 1000°C, whereas in Fe3C, a graphite layer is generally observed to segregate atop (32). Thus, we believe that Mo2C is the best candidate for contacting semiconducting SWNTs.

We confirmed the reaction between carbon nanotubes and the deposited Mo film using time-resolved in situ x-ray diffraction (XRD) (Fig. 1A). To obtain sufficient XRD signal intensity, a thick Mo film (30 nm) was deposited on top of a 200-nm-thick mat of SWNTs sitting on a SiO2/Si substrate (33). The C atoms from the SWNTs started to react with Mo to form Mo2C above ~800°C, as evidenced by the disappearance of Mo (110) peak around 2θ ≈ 47° and the emergence of carbide peaks at 2θ ≈ 40° and 46°, which correspond to the (100) and (101) planes of the Mo2C crystal, respectively. In real devices, the amount of C provided by SWNTs is much smaller than the Mo available in the electrodes. To verify the reaction in this regime, Raman spectroscopy was used to monitor the effect of thermal treatment on a bilayer of SWNTs [~4 nm thick, assembled with the Langmuir-Schaefer method (34)] covered by a semitransparent 8-nm-thick Mo film. Although the structural integrity of exposed SWNTs was not affected in this temperature range under vacuum (fig. S1), the Raman intensity of the characteristic G band of the nanotubes under Mo started to decrease above 750°C and was completely extinguished in samples annealed at 850°C (Fig. 1B), indicating the occurrence of a reaction destroying the SWNT lattice. Energy-dispersive x-ray (EDX) spectroscopy mapping revealed that under the Mo, the C atoms from the SWNTs dispersed into the Mo (Fig. 1, C to E). In a real device structure in which SWNTs are only covered by Mo in the contact region, this dissolution of C in Mo matrix should lead to an abrupt point-like junction between the three-dimensional (3D) Mo electrode and the 1D SWNT channel (Fig. 2, A to B), considering the low diffusion coefficient of Mo resulting from its high melting temperature (26).

Fig. 1 Reaction of carbon nanotubes with Mo thin film.

(A) In situ temperature-variable x-ray diffraction pattern of Mo deposited on a thick nanotube film showing peaks characteristics for Mo and Mo2C. (B) Raman spectra for double-layered nanotubes covered by 8 nm Mo before and after annealed under difference temperatures, showing the characteristic G band of nanotubes and the transverse optical phonon band of crystalline Si substrate. (C and D) False-colored EDX maps of carbon for nanotubes annealed to 850°C without (part C) or with (part D) the Mo film on top. (E) Cross-sectional TEM image showing the profile of the Mo film after annealing as in (D). Scale bars, 20 nm.

Fig. 2 Mo end-contacted SWNT transistors.

(A and B) Schematics showing the conversion from a side-bonded contact (A), where the SWNT is partially covered by Mo, to end-bonded contact (B), where the SWNT is attached to the bulk Mo electrode through carbide bonds while the C atoms from originally covered portion of the SWNT uniformly diffuse out into the Mo electrode. (C) Transfer characteristics of a typical Mo end-contacted single-nanotube transistor built on 20 nm SiNx gate dielectric with a nominal Lch of 60 nm plotted in both linear (black, left axis) and logarithmic (blue, right axis) scales with applied VDS of −0.5 V (filled circles) and −0.05 V (hollow circles). IDS, drain-to-source current. (D) Output characteristics of the device at room temperature (VGS changes from −6 V to 1 V in steps of 1 V). (E) Output characteristics for the same device taken at VGS = −6 V for different temperatures ranging from 297 to 20 K.

Forming such desired end-bonded structure does not guarantee the good electrical quality of the contacts between Mo and the semiconducting SWNT channel. In order to qualify as a good electrical contact, this pointlike Mo-SWNT end contact must exhibit nearly zero barrier and small contact resistance even with a cross-sectional area down to ~1 nm2. To test this, Mo end-contacted FETs with a nominal Lch of 60 nm were made with individual SWNTs deposited from solution. These devices have rather large Mo electrodes (~500 nm wide) and were fabricated on a Si substrate covered by 20 nm thermally robust Si nitride gate dielectric. The transfer characteristics of a representative device are shown in Fig. 2C, with an on/off current ratio up to 107 and a small subthreshold swing of ~100 mV/decade. Its output characteristics (Fig. 2D) reveal other aspects of the excellent device performance, including on-state resistance ~40 kilohm, saturation current near 15 μA, and nearly linear current-voltage characteristics at small drain-to-source bias (VDS). All of these results suggest that high-quality barrier-free contacts were formed. The absence of Schottky barrier was further confirmed with temperature-dependent measurements. The device output characteristics remain unchanged when measured from room temperature to 20 K (Fig. 2E), indicating nearly zero Schottky barrier for hole injection. Although the real contact area is extremely small, these end-bonded contacts demonstrate excellent electrical reliability, with negligible changes in on-state current or on/off current ratio when the device was electrically cycled more than 400 times, under a peak current density above 4 × 108 A cm−2 (fig. S2), presumably because of the formation of robust metal carbide bonds (28).

For truly end-bonded contacts, 2Rc should be independent of contact size. Unlike conventional side contacts, all of the carrier collection should occur at the quasi-0-D interface, with the negligible spreading resistance (fig. S3) (33), so the contact resistance 2Rc should be independent of the physical width of the metal contact Lc. We measured devices with a short Lc of 20 nm made on solution-processed SWNTs and found that ~50% of them exhibited low overall device resistance (below 40 kilohm) (fig. S4), which is comparable with the ratio obtained from devices made with wide contacts. To further confirm the invariance of contact resistance with Lc and verify the formation of an end-bonded contact, we needed to control other factors, in particular the dependence of 2Rc on the SWNT diameter and band gap (16). To do this, we fabricated a series of devices with different Lc on the same long nanotube grown by means of chemical vapor deposition (Fig. 3, A and B). This approach provided precisely defined device geometries with a constant diameter and band gap among devices. The diameter of this particular SWNT was ~1.6 nm (fig. S5) from atomic force microcopy (AFM). The Lch for each device was 60 nm, so that the SWNT channel should be ballistic, and thus the 2Rc could be approximated as the total device resistance minus the quantum resistance of the SWNT channel (RQ = 6.5 kilohm) (16).

Fig. 3 Contact length scaling of Mo end-contacted quasiballistic SWNT transistors.

(A) Schematic and (B) false-colored SEM images of a set of transistors fabricated on the same nanotube, with Lc ranging from 20 to 300 nm. Scale bar, 400 nm. (C) Collection of transfer characteristics from a set of Mo end-contacted single-nanotube transistors with different Lc plotted in both linear (lines, left axis) and logarithmic (symbols, right axis) scales with applied VDS of −0.5 V. (D) Output characteristics of the same devices as in (C) measured at VGS of −6 V. Curves for the device with 20 nm Lc measured with descending VGS at a step of 1 V are also plotted (dashed lines). (E) Plot of 2Rc as a function of Lc for two sets of Mo end-contacted devices (red), with each set on a different nanotube (red circle or diamond represents a set of transistors on the same tube), and the best Pd side-contacted nanotube devices from (21) (black square). Additional Mo end-contacted nanotube devices whose Lc are confined by contact trenches (extracted from Fig. 4F) are shown as blue hexagons. The black dashed curve represents a fitting to the formula of 2Rc = 2ρc/Lc, where ρc is the linear contact resistivity. The red dotted line serves as a visual guide highlighting the invariance of 2Rc for end-bonded contacts.

The transfer characteristics of devices with Lc varying from 20 to 300 nm at the same gate overdrive (VOV, defined as the gate bias VGS applied above the device threshold voltage) (plotted in Fig. 3C) showed no off-state performance difference caused by such wide Lc variation. The values of 2Rc, extracted from the low-field slope of the output curves at high VGS (Fig. 3D), are all in the range of 25 to 35 kilohm per SWNT. Considering that the junction area is merely ~2 nm2, this value corresponds to a contact resistivity as low as 3 × 10−10 ohm cm2, compared with previous best value in the range of 1.5 × 10−9 to 4 × 10−9 ohm cm2 for metal to Si or SWNT contacts (21, 35). In Fig. 3E, the Lc scaling of our devices is compared with one of the best reported Pd side-bonded contacts (21). For side-bonded contacts, because of the distributed nature of SWNT-metal interface, the 2Rc is proportional to the reciprocal of Lc in small contact regime as in the standard transmission line model commonly used for semiconductor devices (19, 36). Mo end-bonded contacts start to outperform Pd side-bonded contacts at dimensions near 20 nm, and we project that the former possesses more than two times the performance advantage for Lc scaled below 10 nm.

As a final demonstration that a Mo end-bonded contact can maintain its low 2Rc and thus serve as the contact scaling solution for future ultimately scaled device technologies, we constructed a SWNT transistor with a physical Lc below 10 nm (a schematic is shown in Fig. 4A; the detailed fabrication flow is depicted in fig. S6). The actual Mo-to-SWNT contacts are confined by the size of SiO2 trenches, similar to the contact vias in standard Si MOSFETs. The corresponding scanning electron microscopy (SEM) and scanning transmission electron microscopy (STEM) images in Fig. 4, B to D, characterize the geometry of the sub–10-nm Lc device, performed after electrical measurements. The cross-sectional STEM image (Fig. 4D) provides information on the sidewall shape of the SiO2 trenches to give an accurate extraction of the effective device Lc to be ~9 nm, which is taken as the average of Lc for source and drain electrodes. Mo nicely filled into these narrow vias. The roughness on the metal top surface is caused by the grain growth induced by this annealing process and can be planarized with a chemical-mechanical polishing process in the real technology integration process flow. Transfer and output characteristics of three devices with effective Lc of 59, 36, and 9 nm made on this SWNT are plotted in Fig. 4, E and F, with their on-current levels consistent with each other, confirming the Lc independence of 2Rc (Fig. 3E). The device with 9 nm Lc performs well with an on-current of >10 μA at only −0.5 V VDS, an on/off current ratio of 104, and extracted overall device resistance in low-bias regime less than 36 kilohm. For a realistic SWNT transistor consisting of a nanotube array with a tube pitch of ~8 nm (5), the effective device contact resistance per width becomes ~240 ohm μm, which satisfies even the most stringent target listed by International Roadmap for Semiconductors up to 1.3 nm technology node in 2028 (37). This end-bonded contact geometry formed through reaction between Mo and nanostructures could readily be extended to improve the Lc scaling behavior of ultrascaled nanoelectronic devices on the basis of other low-dimensional materials including graphene and MoS2. We have only demonstrated p-channel SWNT transistors using p-type end contacts. It will be difficult to form end-bonded n-type contacts to SWNTs in which electrons are directly injected into the conduction band of SWNTs with this carbide formation approach, as metals with low enough work function tend to oxidize first rather than react with C. However, it is still possible to realize n-channel SWNT device operation even with end-bonded contacts to high work function metals through electrostatic doping in the vicinity of the source electrode (10, 38).

Fig. 4 Mo end-contacted quasiballistic SWNT transistors with Lc defined by contact trenches.

(A) Schematic and (B) false-colored SEM image of a set of Mo end-contacted nanotube transistors made on the same nanotube with Lc ranging from ~10 to 60 nm defined by SiO2 contact trenches. The diameter of this particular nanotube is determined to be ~1.7 nm by means of AFM (fig. S5). Scale bar, 400 nm. (C) Top-view SEM image of the ~9 nm effective Lc nanotube transistor at a higher magnification. Scale bar, 100 nm. (D) Cross-sectional high-angle annular dark field-STEM of this device showing the trench profile for the accurate determination of Lc. (E) Collection of transfer characteristics from the set of Mo-contacted nanotube transistors as in (B) with different Lc plotted in both linear (lines, left axis) and logarithmic (symbols, right axis) scales under applied VDS of −0.5 V. (F) Output characteristics of the same devices as in (E) measured at VOV of −7 V. Curves for the device with ~9 nm effective Lc measured with descending VGS at a step of 1 V are also plotted (dashed lines).

Supplementary Materials

www.sciencemag.org/content/350/6256/68/suppl/DC1

Materials and Methods

Figs. S1 to S7

References (3943)

References and Notes

  1. International technology roadmap for semiconductors (ITRS, www.itrs.net) predicts that the device Lch should shrink to ~10 nm by the 2020 time frame, with length of ~9 nm for contacts. For a realistic carbon nanotube transistor consisting of a nanotube array with a tube pitch of ~8 nm, when scaled to Lc of 9 nm the effective device contact resistance per width for best side-bonded Pd contacts becomes ~520 ohm μm, which is two to three times higher than that of current silicon MOSFETs.
  2. Materials and methods are available as supplementary materials on Science Online.
  3. ITRS predicts that overall source/drain parasitic resistance per width should be 256 ohm μm for multigate transistors targeting at high-performance applications at 1.3 nm technology node with a Lc less than 4 nm in 2028. However, no manufacturable solutions are known to keep this resistance level upon scaling beyond even a 7-nm node from 2018.
  4. Acknowledgments: We thank J. Bucchignano for technical assistance with electron-beam lithography. Q. C. conceived and designed the experiments. Q.C., S.-J.H., A.D.F., and J.S.T. performed the experiments. Y.Z. performed STEM and EDX analysis. Z.Z. performed in situ XRD. G.S.T. provided carbon nanotubes. Q.C. wrote the manuscript. All authors discussed the results and commented on the manuscript.
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