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MoS2 transistors with 1-nanometer gate lengths

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Science  07 Oct 2016:
Vol. 354, Issue 6308, pp. 99-102
DOI: 10.1126/science.aah4698

A flatter route to shorter channels

High-performance silicon transistors can have gate lengths as short as 5 nm before source-drain tunneling and loss of electrostatic control lead to unacceptable leakage current when the device is off. Desai et al. explored the use of MoS2 as a channel material, given that its electronic properties as thin layers should limit such leakage. A transistor with a 1-nm physical gate was constructed with a MoS2 bilayer channel and a single-walled carbon nanotube gate electrode. Excellent switching characteristics and an on-off state current ratio of ∼106 were observed.

Science, this issue p. 99

Abstract

Scaling of silicon (Si) transistors is predicted to fail below 5-nanometer (nm) gate lengths because of severe short channel effects. As an alternative to Si, certain layered semiconductors are attractive for their atomically uniform thickness down to a monolayer, lower dielectric constants, larger band gaps, and heavier carrier effective mass. Here, we demonstrate molybdenum disulfide (MoS2) transistors with a 1-nm physical gate length using a single-walled carbon nanotube as the gate electrode. These ultrashort devices exhibit excellent switching characteristics with near ideal subthreshold swing of ~65 millivolts per decade and an On/Off current ratio of ~106. Simulations show an effective channel length of ~3.9 nm in the Off state and ~1 nm in the On state.

As Si transistors rapidly approach their projected scaling limit of ~5-nm gate lengths, exploration of new channel materials and device architectures is of utmost interest (13). This scaling limit arises from short channel effects (4). Direct source-to-drain tunneling and the loss of gate electrostatic control on the channel severely degrade the Off state leakage currents, thus limiting the scaling of Si transistors (5, 6). Certain semiconductor properties dictate the magnitude of these effects for a given gate length. Heavier carrier effective mass, larger band gap, and lower in-plane dielectric constant yield lower direct source-to-drain tunneling currents (7). Uniform and atomically thin semiconductors with low in-plane dielectric constants are desirable for enhanced electrostatic control of the gate. Thus, investigation and introduction of semiconductors that have more ideal properties than Si could lead to further scaling of transistor dimensions with lower Off state dissipation power.

Transition metal dichalcogenides (TMDs) are layered two-dimensional (2D) semiconductors that have been widely explored as a potential channel material replacement for Si (811), and each material exhibits different band structures and properties (1216). The layered nature of TMDs allows uniform thickness control with atomic-level precision down to the monolayer limit. This thickness scaling feature of TMDs is highly desirable for well-controlled electrostatics in ultrashort transistors (3). For example, monolayer and few-layer MoS2 have been shown theoretically to be superior to Si at the sub-5-nm scaling limit (17, 18).

The scaling characteristics of MoS2 and Si transistors as a function of channel thickness and gate length are summarized in Fig. 1. We calculated direct source-to-drain tunneling currents (ISD-LEAK) in the Off state for different channel lengths and thicknesses using a dual-gate device structure (fig. S1) as a means to compare the two materials. MoS2 shows more than two orders of magnitude reduction in ISD-LEAK relative to Si mainly because of its larger electron effective mass along the transport direction (Embedded Image for MoS2 versus Embedded Image for Si [100]) (19), with a trade-off resulting in lower ballistic On current. Notably, ISD-LEAK does not limit the scaling of monolayer MoS2 even down to the ~1-nm gate length, presenting a major advantage over Si [see more details about calculations in the supplementary materials (20)]. Finally, few-layer MoS2 exhibits a lower in-plane dielectric constant (~4) compared with bulk Si (~11.7), Ge (~16.2), and GaAs (~12.9), resulting in a shorter electrostatic characteristic length (λ) as depicted in fig. S2 (21).

Fig. 1 Direct source-to-drain tunneling leakage current.

(A) Normalized direct source-to-drain tunneling leakage current (ISD-LEAK), calculated using the WKB (Wentzel-Kramers-Brillouin) approximation as a function of channel thickness TCH for Si and MoS2 in the Off state. VDS = VDD = 0.43 V from the International Technology Roadmap for Semiconductors (ITRS) 2026 technology node. (B) ISD-LEAK as a function of gate length LG for different thicknesses of Si and MoS2 for the same Off state conditions as Fig. 1A. The dotted line in Fig. 1, A and B represents the low operating power limit for the 2026 technology node as specified by the ITRS.

The above qualities collectively make MoS2 a strong candidate for the channel material of future transistors at the sub-5-nm scaling limit. However, to date, TMD transistors at such small gate lengths have not been experimentally explored. Here, we demonstrate 1D gated, 2D semiconductor field-effect transistors (1D2D-FETs) with a single-walled carbon nanotube (SWCNT) gate, a MoS2 channel, and physical gate lengths of ~1 nm. The 1D2D-FETs exhibit near ideal switching characteristics, including a subthreshold swing (SS) of ~65 mV per decade at room temperature and high On/Off current ratios. The SWCNT diameter d ~ 1 nm for the gate electrode (22) minimized parasitic gate to source-drain capacitance, which is characteristic of lithographically patterned tall gate structures. The ~1-nm gate length of the SWCNT also allowed for the experimental exploration of the device physics and properties of MoS2 transistors as a function of semiconductor thickness (i.e., number of layers) at the ultimate gate-length scaling limit.

The experimental device structure of the 1D2D-FET (Fig. 2A) consists of a MoS2 channel (number of layers vary), a ZrO2 gate dielectric, and a SWCNT gate on a 50-nm SiO2/Si substrate with a physical gate length (LG ~ d) of ~1 nm. Long, aligned SWCNTs grown by chemical vapor deposition were transferred onto a n+ Si/SiO2 substrate (50-nm-thick SiO2) (23), located with a scanning electron microscope (SEM), and contacted with palladium via lithography and metallization. These steps were followed by atomic layer deposition (ALD) of ZrO2 and pick-and-place dry transfer of MoS2 onto the SWCNT covered by ZrO2 (14). Nickel source and drain contacts were made to MoS2 to complete the device. The detailed process flow and discussion about device fabrication is provided in fig. S3.

Fig. 2 1D2D-FET device structure and characterization.

(A) Schematic of 1D2D-FET with a MoS2 channel and SWCNT gate. (B) Optical image of a representative device shows the MoS2 flake, gate (G), source (S), and drain (D) electrodes. (C) False-colored SEM image of the device showing the SWCNT (blue), ZrO2 gate dielectric (green), MoS2 channel (orange), and the Ni source and drain electrodes (yellow). (D) Cross-sectional TEM image of a representative sample showing the SWCNT gate, ZrO2 gate dielectric, and bilayer MoS2 channel. (E) EELS map showing spatial distribution of carbon, zirconium, and sulfur in the device region, confirming the location of the SWCNT, MoS2 flake, and ZrO2 dielectric.

Figure 2B shows the optical image of a representative 1D2D-FET capturing the MoS2 flake, the source and drain contacts to MoS2, and the gate contacts to the SWCNT. The SWCNT and the MoS2 flake can be identified in the false-colored SEM image of a representative sample (Fig. 2C). The 1D2D-FET consists of four electrical terminals; source (S), drain (D), SWCNT gate (G), and the n+ Si substrate back gate (B). The SWCNT gate underlaps the S/D contacts. These underlapped regions were electrostatically doped by the Si back gate during the electrical measurements, thereby serving as n+ extension contact regions. The device effectively operated like a junctionless transistor (24), where the SWCNT gate locally depleted the n+ MoS2 channel after applying a negative voltage, thus turning Off the device.

A cross-sectional transmission electron microscope (TEM) image of a representative 1D2D-FET (Fig. 2D) shows the SWCNT gate, ZrO2 gate dielectric (thickness TOX~5.8 nm), and the bilayer MoS2 channel. The topography of ZrO2 surrounding the SWCNT and the MoS2 flake on top of the gate oxide was flat, as seen in the TEM image. This geometry is consistent with ALD nucleation initiating on the SiO2 substrate surrounding the SWCNT and eventually covering it completely as the thickness of deposited ZrO2 exceeds the SWCNT diameter d (25). The spatial distribution of carbon, zirconium, and sulfur was observed in the electron energy-loss spectroscopy (EELS) map of the device region (Fig. 2E), thus confirming the location of the SWCNT, ZrO2, and MoS2 in the device (fig. S4) (20).

The electrical characteristics for a 1D2D-FET with a bilayer MoS2 channel (Fig. 3) show that the MoS2 extension regions (the underlapped regions between the SWCNT gate and S/D contacts) could be heavily inverted (i.e., n+ state) by applying a positive back-gate voltage of VBS = 5 V to the Si substrate. The ID-VBS characteristics (fig. S5) indicate that the MoS2 flake was strongly inverted by the back gate at VBS = 5 V. The ID-VGS characteristics for the device at VBS = 5 V and VDS = 50 mV and 1 V (Fig. 3A) demonstrate the ability of the ~1-nm SWCNT gate to deplete the MoS2 channel and turn Off the device. The 1D2D-FET exhibited excellent subthreshold characteristics with a near ideal SS of ~65 mV per decade at room temperature and On/Off current ratio of ~106. The drain-induced barrier lowering (DIBL) was ~290 mV/V. Leakage currents through the SWCNT gate (IG) and the n+ Si back gate (IB) are at the measurement noise level (Fig. 3A). The interface trap density (DIT) of the ZrO2-MoS2 interface estimated from SS was ~1.7 × 1012 cm−2 eV−1, which is typical for transferred MoS2 flakes (26) because of the absence of surface dangling bonds (20).

Fig. 3 Electrical characterization and TCAD simulations of 1D2D-FET.

(A) ID-VGS characteristics of a bilayer MoS2 channel SWCNT gated FET at VBS = 5 V and VDS = 50 mV and 1 V. The positive VBS voltage electrostatically dopes the extension regions n+. (B) ID-VDS characteristic for the device at VBS = 5 V and varying VGS. (C) ID-VGS characteristics at VDS = 1 V and varying VBS illustrating the effect of back-gate bias on the extension region resistance, SS, On current, and device characteristics. Electric field contour plots for a simulated bilayer MoS2 device using TCAD in the (D) Off and (F) On state. Electron density plots for the simulated device using TCAD in the (E) Off and (G) On state. The electron density in the depletion region is used to define the LEFF. LEFF ~ d ~ LG in the On state and LEFF > LG in the Off state because of the fringing electric fields from the SWCNT gate.

Figure 3B shows the ID-VDS characteristics at different VGS values and fixed VBS = 5 V. The ID-VGS characteristics depended strongly on the value of VBS, which affects the extension region resistance. The inversion of the extension regions increased with increasing VBS, thus reducing the series resistance and contact resistance and led to an increase in the On current and an improvement in the SS. At more positive values of VBS, VGS had to be more negative in order to deplete the MoS2 channel, which in turn made the threshold voltage (VT)more negative. Above VBS = 1 V, the SS and IOn did not improve any further, and the extension regions were strongly inverted (Fig. 3C). Thus, the 1D2D-FET operated as a short-channel device.

We performed detailed simulations using Sentaurus TCAD to understand the electrostatics of the 1D2D-FET. The Off and On state conditions correspond to (VGS-VT) of –0.3 V and 1.5 V, respectively (which give an On/Off current ratio of ~106). The electric field contour plot (Fig. 3D) in the Off state has a region of low electric field in the MoS2 channel near the SWCNT, indicating that it is depleted. The reduced electron density in the MoS2 channel (Fig. 3E), and the presence of an energy barrier to electrons in the conduction band (fig. S6A) are also consistent with the Off state of the device. The extension regions are still under inversion because of the positive back-gate voltage. The electron density of the MoS2 channel in the depletion region can be used to define the effective channel length (LEFF) of the 1D2D-FET, which is the region of channel controlled by the SWCNT gate (2729). The channel is considered to be depleted if the electron density falls below a defined threshold (nthreshold). The Off state LEFF, defined as the region of MoS2 with electron density n < nthreshold (nthreshold = 1.3 × 105 cm−2), for this simulated 1D2D-FET is LEFF ~ 3.9 nm (Fig. 3E). LEFF is dependent on VGS and the value of nthreshold (fig. S7).

As the device is turned Off, the fringing electric fields from the SWCNT (Fig. 3D) deplete farther regions of the MoS2 channel and thus increase LEFF. The short height of the naturally defined SWCNT gate prevents large fringing fields from controlling the channel and hence achieves a smaller LEFF compared with lithographically patterned gates (fig. S8). The electric field and electron density contours for the device in the On state confirm the strong inversion of the channel region near the SWCNT (Fig. 3, F and G) with LEFF ~ LG = 1 nm. The energy bands in this case are flat in the entire channel region (fig. S6B), with the On state current being limited by the resistance of the extension regions and mainly the contacts. Doped S/D contacts along with shorter extension regions will result in increased On current.

The effect of TOX scaling on short-channel effects like DIBL was also studied using simulations (fig. S9). The electrostatics of the device improves, and the influence of the drain on the channel reduces, as TOX is scaled down to values commensurate with LG. This effect is seen by the strong dependence of DIBL on TOX, thus demonstrating the need for TOX scaling and high-κ (dielectric constant) 2D dielectrics to further enhance the device performance.

The effect of MoS2 thickness on the device characteristics was systematically explored. At the scaling limit of the gate length, the semiconductor channel thickness must also be scaled down aggressively, as described earlier. The electrostatic control of the SWCNT gate on the MoS2 channel decreased with increasing distance from the ZrO2-MoS2 interface. Thus, as the MoS2 flake thickness was increased, the channel could not be completely depleted by applying a negative VGS. Because of this effect, the SS for a 12-nm-thick MoS2 device (~170 mV per decade) was much larger than that of bilayer MoS2 (~65 mV per decade), and as the thickness of MoS2 was increased to ~31 nm, the device could no longer be turned off (Fig. 4A). The experimental SS as a function of MoS2 thickness was qualitatively consistent with the TCAD simulations (Fig. 4B and S10), showing an increasing trend with increasing channel thickness. The unwanted variations in device performance caused by channel thickness fluctuations (Fig. 4B and fig. S10), and the need for low Off state current at short channel lengths (Figs. 1 and 3), thus justify the need for layered semiconductors like TMDs at the scaling limit.

Fig. 4 MoS2 thickness dependence.

(A) Dependence of MoS2 channel thickness on the performance of 1D2D-FET. SS increases with increasing MoS2 channel thickness. (B) Extracted SS from experimental curves and TCAD simulations show increasing SS as channel thickness TCH increases.

TMDs offer the ultimate scaling of thickness with atomic-level control, and the 1D2D-FET structure enables the study of their physics and electrostatics at short channel lengths by using the natural dimensions of a SWCNT, removing the need for any lithography or patterning processes that are challenging at these scale lengths. However, large-scale processing and manufacturing of TMD devices down to such small gate lengths are existing challenges requiring future innovations. For instance, research on developing process-stable, low-resistance ohmic contacts to TMDs, and scaling of the gate dielectric by using high-κ 2D insulators is essential to further enhance device performance. Wafer-scale growth of high-quality films (30) is another challenge toward achieving very-large-scale integration of TMDs in integrated circuits. Finally, fabrication of electrodes at such small scale lengths over large areas requires considerable advances in lithographic techniques. Nevertheless, the work here provides new insight into the ultimate scaling of gate lengths for a FET by surpassing the 5-nm limit (37) often associated with Si technology.

Supplementary Materials

www.sciencemag.org/content/354/6308/99/suppl/DC1

Materials and Methods

Supplementary Text

Figs. S1 to S10

Table S1

References (3144)

References and Notes

  1. Supplementary materials are available on Science Online.
Acknowledgments: S.B.D. and A.J. were supported by the Electronics Materials program funded by the Director, Office of Science, Office of Basic Energy Sciences, Materials Sciences and Engineering Division of the U.S. Department of Energy under contract DE-AC02-05CH11231. A.B.S. was funded by Applied Materials, Inc., and Entegris, Inc., under the I-RiCE program. J.P.L. and J.B. were supported in part by the Office of Naval Research BRC program. J.P.L. acknowledges a Berkeley Fellowship for Graduate Studies and the NSF Graduate Fellowship Program. Q.W. and M.J.K. were supported by the NRI SWAN Center and Chinese Academy of Sciences President’s International Fellowship Initiative (2015VTA031). G.P. and H.-S.P.W. were supported in part by the SONIC Research Center, one of six centers supported by the STARnet phase of the Focus Center Research Program (FCRP) a Semiconductor Research Corporation program sponsored by MARCO and DARPA. A.J., H.-S.P.W., and J.B. acknowledge the NSF Center for Energy Efficient Electronics Science (E3S). A.J. acknowledges support from Samsung. The authors acknowledge the Molecular Foundry, Lawrence Berkeley National Laboratory for access to the scanning electron microscope. The authors acknowledge H. Fahad for useful discussions about the analytical modeling. All data are reported in the main text and supplementary materials.
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