Dirac-source field-effect transistors as energy-efficient, high-performance electronic switches

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Science  27 Jul 2018:
Vol. 361, Issue 6400, pp. 387-392
DOI: 10.1126/science.aap9195

Cooler electrons for transistors

The operating power of field-effect transistors is constrained in part by the minimum change in voltage needed to change the current output. This subthreshold swing (SS) limit is caused by hotter electrons from a thermal electron source leaking over the potential of the gate electrode. Qiu et al. show that graphene can act as a Dirac source that creates a narrower distribution of electron energies. When coupled to a carbon nanotube channel, the decrease in SS would allow the supply voltage to be decreased from 0.7 to 0.5 volts.

Science, this issue p. 387


An efficient way to reduce the power consumption of electronic devices is to lower the supply voltage, but this voltage is restricted by the thermionic limit of subthreshold swing (SS), 60 millivolts per decade, in field-effect transistors (FETs). We show that a graphene Dirac source (DS) with a much narrower electron density distribution around the Fermi level than that of conventional FETs can lower SS. A DS-FET with a carbon nanotube channel provided an average SS of 40 millivolts per decade over four decades of current at room temperature and high device current I60 of up to 40 microamperes per micrometer at 60 millivolts per decade. When compared with state-of-the-art silicon 14-nanometer node FETs, a similar on-state current Ion is realized but at a much lower supply voltage of 0.5 volts (versus 0.7 volts for silicon) and a much steeper SS below 35 millivolts per decade in the off-state.

The need for extended time of operation for devices powered by batteries has changed the electronic industry (14). Minimal power consumption may be accomplished by reducing the supply voltage VDD and by designing transistors with steeper subthreshold swing (SS) so that they could be switched from off-state to on-state at faster rates (57). However, conventional Si complementary metal oxide semiconductor (CMOS) field-effect transistors (FETs) are constrained to a 60 mV/decade minimum constraint on SS at room temperature (2) because in a typical n-type FET, electrons in the source are prevented from flowing to the drain by a potential barrier (Fig. 1A) that can be tuned by the gate voltage. The electrons in the source have an energy distribution (usually a thermal Boltzmann distribution) that spreads to the values exceeding the potential barrier created by the gate, which sets a 60 mV/decade limit on SS.

Fig. 1 Electron density distribution and characteristics of normal and Dirac sources.

(A and B) Schematic band structure, density of states, electron density, and thermionic electron emission over a potential barrier in the conduction channel for a normal source with a subexponential decaying of electron density over the potential barrier (A) and a Dirac source with a superexponential decaying and thus a more narrowly localized electron density around the Fermi level (B). The solid line in n(E) represents a Boltzmann distribution with exponential decaying tail toward higher energy; n(E) represents density of electrons. (C) Comparison of electron density distributions between normal sources, based on 3D semiconductor (green curve) and on 2D material (black curve), and a Dirac source based on graphene; the blue curve shows increasingly more localized electron distribution around the Fermi surface for graphene. (D) Schematic transfer characteristics of a conventional FET with a normal source and thus 60 mV/decade–limited subthreshold swing (SS), and a DS-FET with a Dirac source and much steeper SS. Insets are electron density distributions for a normal source (green) and Dirac source (blue), and thermionic electron emission over the potential barrier at low bias (off-state, lower inset) and high bias (on-state, upper inset).

Scaling VDD < 0.5 V while maintaining a high on-state current Ion and low off-state current Ioff will require transistors with a different operation mechanism. These devices include tunnel transistors (T-FETs) (6, 7), impact ionization FETs (i-FETs) (8), and positive feedback and negative gate capacitance FETs (NC-FETs) (911). T-FETs have emerged as the most promising alternative, with the potential to overcome the thermally limited SS of 60 mV/decade by using a supply voltage below 0.5 V, thereby offering substantial power dissipation savings. However, all fabricated T-FETs have severely limited on-state current (typically lower than 10 μA/μm), and the steepest switching slope SS of sub–60 mV/decade is usually not sustained across the entire subthreshold region (1216). Other kinds of sub–60 mV/decade transistors also suffer from vital drawbacks such as large hysteresis (10) and limited speed, stability, or voltage scalability (8, 17).

We now consider introducing a “Dirac source” (DS) for the conventional FET, which is a “cold electron source” without a long thermal tail above the potential barrier in the channel. If the density of states (DOS) of electrons in the source is a decreasing function of energy, the density of electrons will decrease superexponentially with increasing energy (Fig. 1B and blue curve in Fig. 1C), resulting in a much more localized electron distribution around the Fermi level EF. This DS still permits a large thermionic current in the on-state, as in a conventional FET (see Fig. 1D).

We chose graphene as the DS material. Graphene has a linear band dispersion, and when suitably doped it may yield a superexponentially decreasing electron density with increasing energy toward the Dirac point (Fig. 1B). In addition to providing a sharply localized carrier distribution around EF, the DS should also have a clean interface with the channel and suitably aligned EF and band edges. For a graphene source, semiconducting single-walled carbon nanotubes (SWCNTs) can form a highly transparent interface for the injection of carriers when the DS-FET is in its on-state, but they create a large barrier to block the leakage current when in its off-state. Given their extremely high mobility for both electrons and holes and their ultrathin body, CNTs have been used for building conventional FETs that show better performance than state-of-the-art Si MOSFETs when scaled down to the sub–10 nm technology node (1824). When combined with graphene, a CNT FET could be scaled down to 5 nm without suffering noticeable short-channel effect, and a near–thermionic limit SS value of 60 mV/decade was demonstrated (24).

Our DS-FET device (Fig. 2A) consisted of three components: (i) a semiconducting SWCNT channel, (ii) a suitably doped “cold” graphene DS (GDS), and (iii) a highly efficient Y2O3/Pd top gate stack to provide electrostatics control of the channel (see fig. S1). The device must set EF in the n-branch of the GDS for p-type FETs or in the p-branch for n-type FETs, and the Schottky barrier between the graphene and CNT must be small or even zero when the device is switched to on-state (blue region in fig. S1B), because a large Schottky barrier will dominate the carrier injection process (25).

Fig. 2 Structure and performance of a DS-FET with a control gate.

(A) Schematic diagram showing a DS-FET with a control gate in addition to the normal gate. (B) Top-view SEM image of a DS-FET. Scale bar, 200 nm. The devices are fabricated on doped Si substrate covered with a 300-nm layer of SiO2. (C) Schematic diagrams illustrating the off-state of the DS-FET. (D) Transfer characteristics of a typical DS-FET at different values of VCG. Circles, experimental results; curves, simulated results. Green and blue denote results obtained at VCG = 1.5 V and 0 V, respectively. Insets are schematic band edge profiles for fitted data situations. (E) Subthreshold swing phase diagram as a function of the control gate voltage, showing the condition for the appearance of sub–60 mV/decade behavior. The orange dashed line is a guiding curve of SS-VCG for DS-FETs according to simulation results. Each colored star represents one DS-FET at the corresponding VCG. (F) Temperature-dependent SS of a typical DS-FET measured at temperatures between 77 and 300 K. VCG was set at 2 V to keep the device in Dirac-source mode. SS varied by more than 100% from 77 to 300 K. In all measurements, the substrate was biased with –20 V to keep the ungated region near the drain open.

We used a control gate (CG) to tune the Fermi level (EFS) of the GDS (Fig. 2, A and B). In Fig. 2A, the DS FET was designed to be a p-type FET because the CNT channel contacts a Pd (p-type) drain. In Fig. 2C, we show a transport model based on a calculated band-edge profile using full quantum transport simulations (detailed in fig. S2). Beneath the control gate, the graphene is n-doped. When biased with a drain voltage, electrons are injected from the n-doped graphene source to the drain, passing through an n-p junction in graphene via tunneling before reaching a CNT bulk barrier, the height and width of which can be tuned by a gate on top of the CNT. In graphene, the n-p tunneling is Klein tunneling and is essentially transparent (26, 27). Thus, the device current was mainly modulated by the top gate via varying the height and width of the CNT bulk barrier.

In the off-state, the CNT bulk barrier width was >100 nm and the tunneling current through this barrier was negligible; the dominating contribution to the off-state current originated from the thermal emission current over the CNT bulk barrier (Fig. 2C). During the switching-off process, the barrier height for hole injection increased and simultaneously the DOS of the n-doped graphene source over the top of the barrier decreased toward the Dirac point (see Fig. 2C and fig. S3). Thus, the thermally activated hole density over the barrier in the graphene source decreased with decreasing energy superexponentially, leading to a slope steeper than 60 mV/decade in the DS-FET (Fig. 2C). To verify the dominating operation mechanism for sub–60 mV/decade SS in DS-FETs, we simulated the device operation theoretically using both analytical and numerical methods (see supplementary materials and fig. S1). A ballistic FET model with an n-doped graphene and Pd-contacted CNT was used to fit the measured transfer characteristics (Fig. 2D), showing excellent agreement between experimental and theoretical results.

The two transfer characteristics shown in Fig. 2D correspond to two operation modes of the CNT FET with graphene as the source (for more transfer characteristics, see fig. S4). When the control gate was set at zero (VCG = 0 V), the graphene source was usually p-doped; the carrier DOS increased with increasing VCG toward the off-state (Fig. 2D, right inset). The device worked as a conventional FET with a SS of 67 mV/decade. However, applying a large positive VCG to the control gate tuned the GDS to its n-branch (Fig. 2D, left inset). The carrier DOS in the GDS decreased with increasing VCG toward off-state. The transistor now had a SS of 46 mV/decade at room temperature (Fig. 2D, green curve).

Extensive measurements were then carried out on the dependence of SS on VCG for multiple DS-FETs. Figure 2E defines the region in which the CNT FET works as a DS-FET, yielding <60 mV/decade, and the main trend of experimental results is captured very well by our model simulations (fig. S1B). When in DS-FET mode, the transfer characteristics of a typical FET were measured at various temperatures T between 77 and 300 K (fig. S5A), and the extracted SS (Fig. 2F) showed a linear dependence on T, as predicted by theoretical simulations (see fig. S5B). The linear SS-T relation further confirmed that the main mechanism for electron injection over the potential barrier at subthreshold region is thermal emission rather than band-to-band tunneling (BTBT), because for BTBT SS shows much weaker T dependence (2, 28). Tunneling assisted by phonons and mid-gap trap states may occur in T-FETs, resulting in T-dependent SS (29). In these T-FETs, SS varies weakly with T (within a few percent from 100 to 300 K) and/or becomes much greater than 60 mV/decade at room temperature. Trap states may act as stepping stones in these devices that lead to band-to-band tunneling in off-state and degrade SS (29, 30).

In real applications, FETs with additional control gates are undesirable because this structure introduces additional supply burden and is also not scalable. An alternative compact DS-FET structure (Fig. 3A) has a chemically doped GDS. The Pd film was patterned as the drain contact to define the polarity of the FET as p-type (18). The graphene was intentionally doped during the chemical vapor deposition growth process (31), and the Dirac point voltage of the as-grown graphene was distributed around –50 V (see fig. S6A) for the group of samples used in this work, thereby confirming that the graphene was effectively n-doped. Part of the graphene source and CNT channel are beneath the top gate, and an ultrathin Y2O3 is used as the gate dielectric with an equivalent oxide thickness of 1.5 nm (32). More than 50 such DS-FETs were fabricated; the SEM image of a typical DS-FET is shown in Fig. 3B. Transfer characteristics of the DS-FET (Fig. 3C) demonstrate the sub–60 mV/decade subthreshold behavior of this device. At the subthreshold voltage, the transistor presents a SS of 35 mV/decade at room temperature at both low bias (Vds = –0.1 V) and high bias (Vds = –0.5 V). Moreover, the sub–60 mV SS behavior was measured for both sweeping directions of Vgs and showed negligible hysteresis (see fig. S7). The devices achieved an average SS < 60 mV/decade over four decades of current (see Fig. 3E and fig. S7) and can thus meet the requirement set by the International Technology Roadmap for Semiconductors (ITRS) (4).

Fig. 3 Structure and performance of DS-FETs with chemically doped Dirac sources.

(A) Schematic diagrams illustrating the structure of a DS-FET, with a chemically n-doped graphene source and Pd-contacted drain. (B) Top-view SEM image showing a DS-FET. Scale bar, 500 nm. (C) Transfer characteristics of a typical DS-FET with Vds = –0.1 V and –0.5 V. The substrate was biased with –20 V. (D) Statistical distribution of SS for 43 DS-FETs with chemically doped graphene as the Dirac source. (E) Transfer characteristics for some representative DS-FETs with Vds = –0.1 V and average SS ranging from 40 to 50 mV/decade. (F) Transfer characteristics of three extremely scaled DS-FETs with channel length of about 15 nm and at bias of –0.1 V.

In addition, the DS-FET based on a single CNT can provide high on-state current of up to 6.5 μA at VDS = –0.5 V, which is orders of magnitude higher than that observed in a tunnel FET based on a single CNT (28, 33). The DS-FET also exhibits much suppressed ambipolar characteristics relative to conventional top-gated CNT FETs (34), presenting a large current on/off ratio of >106 at Vds = –0.5 V. More than 40 DS-FETs have been successfully fabricated with sub–60 mV/decade SS, and the statistical distribution of SS shown in Fig. 3D demonstrates that most devices (32 devices) exhibited SS < 50 mV/decade at room temperature. The transfer characteristics of nine representative devices are plotted in Fig. 3E.

Because miniaturization is an important issue for large-scale integrated circuits (ICs), we fabricated DS-FETs with ultrashort channel lengths of <15 nm (see figs. S8 and S9 for the relevant structure and fabrication process of the extremely scaled DS-FETs); Fig. 3F shows measurement results for three such DS-FETs with SS < 60 mV/decade. The short-channel DS-FETs showed very high on-state current of >10 μA per CNT (fig. S10), which is similar to that achieved in the best reported high-performance p-type conventional CNT FETs (18).

The DS-FET transistor can achieve higher performance and lower dissipation than the most advanced Si CMOS FETs at lower supply voltage. Pure semiconducting CNT arrays with high density (e.g., 125 tubes/μm) have been considered as a good choice for channel material to construct scalable FETs with performance exceeding that of the best Si CMOS FETs (20). We projected the performance of DS-FETs based on a CNT array (Fig. 4A) by normalizing the experimental data on single CNTs and assuming a CNT array density of 125 tubes/μm. The key challenge for realizing high-density CNT array–based DS-FETs results mainly from the nonuniformity of CNTs in the array and their contacts to graphene. Identical CNTs with the same chirality and highly uniform contacts to graphene are needed to retain the threshold voltage of every CNT in the channel within a required narrow range. Ideally, a high-performance FET should have high on-state current Ion and large current on/off ratio at small supply voltage. Figure 4B compares the on-state current Ids and on/off ratio of our DS-FETs and that of state-of-the-art Si MOSFETs, the best T-FETs, and NC-FETs (with VDD < 1 V) (3546). For the same on/off ratio, two representative DS-FETs (blue and red lines) at VDD = 0.5 V show Ids values similar to that of the best Si p-type MOSFET (Intel 14-nm technology node) (35) driven by VDD = 0.7 V, which is 10 to 100 times that of the most advanced III-V nanowire-based heterojunction T-FETs (13, 36) and much greater than that of the best reported NC-FETs (3843).

Fig. 4 Comparison of DS-FETs, state-of-the-art T-FETs, NC-FETs, and Intel 14-nm MOSFETs.

(A) Schematic diagram illustrating the structure of a DS-FET with CNT array as the channel. (B) On-state current Ids versus on/off current ratio for DS-FETs, state-of-the-art T-FETs, NC-FETs, and Intel 14-nm MOSFETs. Red and blue squares denote two typical DS-FETs; open black circles represent Intel 14-nm HP (high performance), SP (standard performance), and ULP (ultralow-power) MOSFETs (35); open green circles, III-V NW T-FET (13); solid green circles, MoS2-Ge T-FET (36); solid orange circles, squares, pentagons, hexagon, diamond, and triangles, typical NC-FETs with VDD < 1 V (3843). (C) Subthreshold swing versus Ids. I60 values in the yellow region are for T-FETs (16); those in the cyan region are for NC-FETs with hysteresis (H) smaller than 0.5 V; and those in the green region are for NC-FETs with H larger than 1 V (3845). The red, green, blue, and purple curves with solid symbols at the upper right represent four different DS-FETs. The black curves with different open symbols at the left represent different T-FETs (16). (D) Comparison between a 400-nm DS-FET (125 CNTs/μm) and a commercial Intel 14-nm Si MOSFET. The Si MOSFET (black) was powered by 0.7 V (35); the DS-FET (red) was powered by a low bias of 0.5 V.

An important figure of merit—I60, the current when the subthreshold swing SS equals 60 mV/decade—accounts for both switching and device on-state characteristics (37). Higher values of I60 correspond to higher on-state current and lower average SS. To benchmark the performance of sub–60 mV/decade devices by using I60, we plot SS-Ids relations of the best published T-FETs, NC-FETs, and our CNT-based DS-FETs in Fig. 4C. For a sub–60 mV/decade device to have a performance comparable to that of the conventional FET, the desired target value of I60 for sub–60 mV/decade devices is in the range 1 to 10 μA/μm at VDD below 0.5 V. However, all the reported T-FETs have I60 values that are typically two orders of magnitude lower than the target (16); in particular, the most advanced InAs/Si nanowire (46) T-FET has an I60 of 0.02 μA/μm at Vds = 1 V. As a comparison, CNT-based DS-FETs typically have I60 values in the range 1 to 40 μA/μm at Vdd = –0.5 V, which meets the I60 challenge for sub–60 mV/decade devices.

Additional challenges for T-FETs include optimization of the device architecture for high Ion combined with an average SS lower than 60 mV/decade over at least four decades. The representative transfer characteristics shown in Fig. 3E amply demonstrate that the sub–60 mV/decade region of CNT-based DS-FETs covers more than four decades of current, meeting the target of ITRS for sub–60 mV/decade transistors. Although some NC-FETs show high I60 values in the range 1 to 40 μA/μm (Fig. 4C), large hysteresis (larger than 1 V) remains the main challenge for their applications in ICs. For these reported NC-FETs with small hysteresis (<0.5 V), I60 is usually lower than 1 μA/μm (3845). As a result, high performance and small hysteresis have not been achieved by the same NC-FET.

Figure 4D shows a direct comparison between the CNT array–based DS-FET (with a gate length of 400 nm) and state-of-the-art Si MOSFET (Intel 14-nm technology) (35). The 400-nm CNT DS-FET exhibited an Ion value similar to that of the 14-nm Si MOSFET, but with much steeper SS (with an average value of about 50 mV/decade over four decades of current) and much lower supply voltage (0.5 V versus 0.7 V). The power dissipation of modern ICs depends strongly on supply voltage (which is proportional to VDD3). The lowering in VDD from 0.7 V to <0.5 V with DS-FETs will reduce power dissipation better than state-of-the-art Si-based computer chips while maintaining similar high performance.

Although we only demonstrated p-type DS FETs, according to the symmetric energy band (19) we could realize an n-type DS-FET based on CNT by using p-doped graphene as the source and Sc as the drain. In principle, it is possible to realize complementary DS-FETs following procedures similar to those outlined here. CNT provides an excellent conduction channel for DS-FET, but the key to the realization of sub–60 mV/decade SS in DS-FETs is not the CNT channel. In principle, GDS may also be combined with other semiconductor channel materials [e.g., semiconducting nanowires, two-dimensional (2D) semiconductors, or even conventional bulk semiconductors] to simultaneously achieve sub–60 mV/decade SS and high Ion. The DS-FET may thus be used as a general device or building block for future ICs with sub–0.5 V power supply.

Supplementary Materials

Materials and Methods

Figs. S1 to S10

References (4761)

References and Notes

Acknowledgments: Funding: Supported by National Science Foundation of China grant 61621061, National Key Research & Development Program grants 2016YFA0201901 and 2016YFA0201902, and Beijing Municipal Science and Technology Commission grants D171100006617002 1-2. Also supported by University Grant Council contract AoE/P-04/08 of the Government of HKSAR (J.W., F.L., and H.G.) and NSERC of Canada (H.G.). We thank CalcuQuebec and Compute Canada for computation facilities. Author contributions: L.-M.P. and Z.Z. proposed and supervised the project; Z.Z., C.Q., and L.-M.P. designed the experiment; C.Q. performed the device fabrication and characterization; M.X. grew the nanotubes; B.D., L.L., and H.P. grew the graphene; F.L., C.Q., L.X., Z.Z., J.W., and H.G. built the model and simulated the devices; Z.Z., C.Q., and L.-M.P. analyzed the data and co-wrote the manuscript; and all authors discussed the results and commented on the manuscript. Competing interests: The authors declare no competing financial interests. Data and materials availability: All data needed to evaluate the conclusions in the paper are present in the paper or the supplementary materials.

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