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Controlled crack propagation for atomic precision handling of wafer-scale two-dimensional materials

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Science  09 Nov 2018:
Vol. 362, Issue 6415, pp. 665-670
DOI: 10.1126/science.aat8126
  • Fig. 1 Layer-resolved splitting (LRS) of 2D materials.

    (A) Schematic illustration explaining the LRS process for 2D materials. ML, monolayer. (B) Modeling of energy release rate according to applied moment. (Ni thickness: 600 nm). Γ, interfacial toughness. (C) Schematics of crack progression during LRS for initial exfoliation of entire 2D materials from sapphire wafer (left) and exfoliation of the bottom monolayer 2D material (right). (D) Raman intensity mapping at the E12g peak (353 cm−1) of WS2 grown on a sapphire substrate, with laser wavelength and power of 532 nm and 2 mW in continuous waveform, respectively, where the spatial resolution is 2 μm. a.u., arbitrary units. (E) AFM topology taken from the top of as-grown 4-nm-thick WS2 on the sapphire wafer. (F) Raman mapping image showing the intensity of the E12g peak (353 cm−1) on sapphire substrate after exfoliation of the WS2 layer, with laser wavelength and power of 532 nm and 2 mW, respectively. (G) AFM topology taken from the bottom of WS2 layer after exfoliation. Scale bars for Raman mapping images and AFM topology images are 2 μm and 50 nm, respectively.

  • Fig. 2 Wafer-scale monolayer 2D material obtained by LRS process.

    (A) Optical image of 5-cm wafer-scale WS2 monolayer on 20.3-cm oxidized Si wafer obtained through the LRS process. (B) Macrograph of 5-cm wafer-scale WS2 monolayer. (C) AFM image and height profile of the WS2 monolayer transferred on SiO2/Si wafer. Scale bar: 1 μm. (D) Representative PL spectra of as-exfoliated 4-nm-thick WS2 (blue line) and monolayer WS2 obtained by LRS process (red line), in which the PL spectrum for 4-nm-thick WS2 is multiplied by a factor of 10 to show the clear peak position. (E) Wafer-scale PL mapping image at 1.99 eV of WS2 on the SiO2/Si wafer, where the spatial resolution is 2 mm. (F) Large-scale (1 mm by 1 mm) PL intensity map from 1.99 eV for WS2 on SiO2, where the spatial resolution is 50 μm (see fig. S6 for 1-μm resolution map). All PL spectra were taken at the same laser power (2 mW) and wavelength (532 nm).

  • Fig. 3 Split of thick 2D materials into many monolayers via LRS process and their characterization.

    (A, C, E, G, and I) Optical micrographs and (B, D, F, H, and J) plan-view SEM images for as-exfoliated thick WS2 [(A) and (B)] and monolayers of WS2 obtained by the first [(C) and (D)], second [(E) and (F)], third [(G) and (H)], and last [(I) and (J)] LRS processes, respectively. The monolayers are all transferred on 90-nm-thick SiO2/Si substrates. (K) Representative PL spectra for as-exfoliated thick WS2 (black line) multiplied by a factor of 10 to show the clear peak position, as well as monolayers of WS2 obtained by the first (red line), second (green line), and third (blue line) LRS processes. All PL spectra were taken at the same laser power (2 mW) and wavelength (532 nm). Scale bars for optical microscopy images and plan-view SEM images are 50 μm and 400 nm, respectively.

  • Fig. 4 Wafer-scale 2D heterostructures.

    PL mapping images at 1.99 eV of (A) a double-layer (2 ML) h-BN/monolayer (1 ML) WS2/2 ML h-BN heterostructure fabricated by quasi-dry stacking, (B) 1 ML WS2 on SiO2 made by quasi-dry transfer, (C) a 2 ML h-BN/1 ML WS2/2 ML h-BN heterostructure formed by wet stacking, and (D) 1 ML WS2 on SiO2 made by wet stacking. (E) Representative PL spectra of all different structures fabricated by different methods. All PL spectra were taken at the same laser power (2 mW) and wavelength (532 nm). (F) Schematic of a MoS2-based field effect transistor (FFT). (G) Macrograph of 10-by-10 FET arrays integrated on a SiO2/Si wafer with 1-cm–by–1-cm size. Inset shows micrograph of an individual device. Scale bar: 100 μm. The device area is defined by the gap between source (S) and drain (D) electrodes. G, gate. (H) Representative drain current–gate voltage (IDVG) characteristics of MoS2-based FETs at drain voltage (VDS) = 1 V. (I) 2D color maps of hysteresis voltage extracted from IDVG curves at VDS = 1 V in transistor arrays made without h-BN (left) and with h-BN (right).

Supplementary Materials

  • Controlled crack propagation for atomic precision handling of wafer-scale two-dimensional materials

    Jaewoo Shim, Sang-Hoon Bae, Wei Kong, Doyoon Lee, Kuan Qiao, Daniel Nezich, Yong Ju Park, Ruike Zhao, Suresh Sundaram, Xin Li, Hanwool Yeon, Chanyeol Choi, Hyun Kum, Ruoyu Yue, Guanyu Zhou, Yunbo Ou, Kyusang Lee, Jagadeesh Moodera, Xuanhe Zhao, Jong-Hyun Ahn, Christopher Hinkle, Abdallah Ougazzaden, Jeehwan Kim

    Materials/Methods, Supplementary Text, Tables, Figures, and/or References

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    • Materials and Methods
    • Figs. S1 to S24
    • References

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