RT Journal Article
SR Electronic
T1 A million spiking-neuron integrated circuit with a scalable communication network and interface
JF Science
JO Science
FD American Association for the Advancement of Science
SP 668
OP 673
DO 10.1126/science.1254642
VO 345
IS 6197
A1 Merolla, Paul A.
A1 Arthur, John V.
A1 Alvarez-Icaza, Rodrigo
A1 Cassidy, Andrew S.
A1 Sawada, Jun
A1 Akopyan, Filipp
A1 Jackson, Bryan L.
A1 Imam, Nabil
A1 Guo, Chen
A1 Nakamura, Yutaka
A1 Brezzo, Bernard
A1 Vo, Ivan
A1 Esser, Steven K.
A1 Appuswamy, Rathinakumar
A1 Taba, Brian
A1 Amir, Arnon
A1 Flickner, Myron D.
A1 Risk, William P.
A1 Manohar, Rajit
A1 Modha, Dharmendra S.
YR 2014
UL http://science.sciencemag.org/content/345/6197/668.abstract
AB Computers are nowhere near as versatile as our own brains. Merolla et al. applied our present knowledge of the structure and function of the brain to design a new computer chip that uses the same wiring rules and architecture. The flexible, scalable chip operated efficiently in real time, while using very little power.Science, this issue p. 668 Inspired by the brain’s structure, we have developed an efficient, scalable, and flexible non–von Neumann architecture that leverages contemporary silicon technology. To demonstrate, we built a 5.4-billion-transistor chip with 4096 neurosynaptic cores interconnected via an intrachip network that integrates 1 million programmable spiking neurons and 256 million configurable synapses. Chips can be tiled in two dimensions via an interchip communication interface, seamlessly scaling the architecture to a cortexlike sheet of arbitrary size. The architecture is well suited to many applications that use complex neural networks in real time, for example, multiobject detection and classification. With 400-pixel-by-240-pixel video input at 30 frames per second, the chip consumes 63 milliwatts.